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    Pooled DRAM System Enabled by Monolithic In-Package Optical I/O
    1.
    发明申请
    Pooled DRAM System Enabled by Monolithic In-Package Optical I/O 有权

    公开(公告)号：US20210257021A1

    公开(公告)日：2021-08-19

    申请号：US17175678

    申请日：2021-02-14

    申请人： Ayar Labs, Inc.

    发明人： Roy Edward Meade ,  Vladimir Stojanovic ,  Chen Sun ,  Mark Wade ,  Hugo Saleh ,  Charles Wuischpard

    IPC分类号： G11C11/42 ,  G11C5/04 ,  G11C5/06

    摘要： A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.

    Pooled DRAM system enabled by monolithic in-package optical I/O
    2.
    发明授权
    Pooled DRAM system enabled by monolithic in-package optical I/O 有权

    公开(公告)号：US11233580B2

    公开(公告)日：2022-01-25

    申请号：US17175678

    申请日：2021-02-14

    申请人： Ayar Labs, Inc.

    发明人： Roy Edward Meade ,  Vladimir Stojanovic ,  Chen Sun ,  Mark Wade ,  Hugo Saleh ,  Charles Wuischpard

    IPC分类号： G11C5/04 ,  G11C5/06 ,  G11C11/42 ,  H04B10/80 ,  H04B10/516

    摘要： A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.

    Remote Memory Architectures Enabled by Monolithic In-Package Optical I/O
    4.
    发明申请
    Remote Memory Architectures Enabled by Monolithic In-Package Optical I/O 有权

    公开(公告)号：US20210258078A1

    公开(公告)日：2021-08-19

    申请号：US17175677

    申请日：2021-02-14

    申请人： Ayar Labs, Inc.

    发明人： Roy Edward Meade ,  Vladimir Stojanovic ,  Chen Sun ,  Mark Wade ,  Hugo Saleh ,  Charles Wuischpard

    IPC分类号： H04B10/80 ,  H04B10/516

    摘要： A remote memory system includes a substrate of a multi-chip package, an integrated circuit chip connected to the substrate, and an electro-optical chip connected to the substrate. The integrated circuit chip includes a high-bandwidth memory interface. An electrical interface of the electro-optical chip is electrically connected to the high-bandwidth memory interface. A photonic interface of the electro-optical chip is configured to optically connect with an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals received through the electrical interface from the high-bandwidth interface into outgoing optical data signals. The optical macro transmits the outgoing optical data signals through the photonic interface to the optical link. The optical macro also converts incoming optical data signals received through the photonic interface into incoming electrical data signals. The optical macro transmits the incoming electrical data signals through the electrical interface to the high-bandwidth memory interface.

    Pooled Memory System Enabled by Monolithic In-Package Optical I/O
    8.
    发明申请
    Pooled Memory System Enabled by Monolithic In-Package Optical I/O 有权

    公开(公告)号：US20220148627A1

    公开(公告)日：2022-05-12

    申请号：US17583967

    申请日：2022-01-25

    申请人： Ayar Labs, Inc.

    发明人： Roy Edward Meade ,  Vladimir Stojanovic ,  Chen Sun ,  Mark Wade ,  Hugo Saleh ,  Charles Wuischpard

    IPC分类号： G11C5/04 ,  G11C5/14 ,  G02B6/42

    摘要： A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.