公开(公告)号：US20100156497A1

公开(公告)日：2010-06-24

申请号：US12710928

申请日：2010-02-23

申请人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

发明人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

IPC分类号： H03L5/00

CPC分类号： H03M3/488

摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

摘要翻译： 用于连续时间Σ-Δ模数转换器的共模转换的系统和方法。 一个实施例包括具有耦合到差分信号输入的RC网络的环路滤波器，耦合到环路滤波器的Gm-C /量化器/ DAC电路（GQD），耦合到GQD的信号输入的共模电平调整电路， 以及耦合到GQD和共模电平调整电路的调谐电路。 GQD评估由RC网络提供的输入信号，计算经滤波的输入信号和反馈量化信号之间的差异以产生误差信号，测量误差信号，并用Σ-Δ噪声整形补偿误差信号。 共模电平调节电路将差分输入信号的共模电平改变为基本上等于期望的共模电平，并且调谐电路基于两者之间的差异向共模电平调整电路提供补偿电压 共模级别。

公开(公告)号：US20080238746A1

公开(公告)日：2008-10-02

申请号：US11729487

申请日：2007-03-29

申请人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

发明人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

IPC分类号： H03M3/00

CPC分类号： H03M3/488

摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

摘要翻译： 用于连续时间Σ-Δ模数转换器的共模转换的系统和方法。 一个实施例包括具有耦合到差分信号输入的RC网络的环路滤波器，耦合到环路滤波器的Gm-C /量化器/ DAC电路（GQD），耦合到GQD的信号输入的共模电平调整电路， 以及耦合到GQD和共模电平调整电路的调谐电路。 GQD评估由RC网络提供的输入信号，计算经滤波的输入信号和反馈量化信号之间的差异以产生误差信号，测量误差信号，并用Σ-Δ噪声整形补偿误差信号。 共模电平调节电路将差分输入信号的共模电平改变为基本上等于期望的共模电平，并且调谐电路基于两者之间的差异向共模电平调整电路提供补偿电压 共模级别。

公开(公告)号：US08390496B2

公开(公告)日：2013-03-05

申请号：US12710889

申请日：2010-02-23

申请人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

发明人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

IPC分类号： H03M1/66

CPC分类号： H03M3/488

摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network. computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

摘要翻译： 用于连续时间Σ-Δ模数转换器的共模转换的系统和方法。 一个实施例包括具有耦合到差分信号输入的RC网络的环路滤波器，耦合到环路滤波器的Gm-C /量化器/ DAC电路（GQD），耦合到GQD的信号输入的共模电平调整电路， 以及耦合到GQD和共模电平调整电路的调谐电路。 GQD评估由RC网络提供的输入信号。 计算经过滤波的输入信号和反馈量化信号之间的差异，以产生误差信号，测量误差信号，并用Σ-Δ噪声整形来补偿误差信号。 共模电平调节电路将差分输入信号的共模电平改变为基本上等于期望的共模电平，并且调谐电路基于两者之间的差异向共模电平调整电路提供补偿电压 共模级别。

公开(公告)号：US08120425B2

公开(公告)日：2012-02-21

申请号：US12710928

申请日：2010-02-23

申请人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

发明人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

IPC分类号： H03F3/45

CPC分类号： H03M3/488

摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

摘要翻译： 用于连续时间Σ-Δ模数转换器的共模转换的系统和方法。 一个实施例包括具有耦合到差分信号输入的RC网络的环路滤波器，耦合到环路滤波器的Gm-C /量化器/ DAC电路（GQD），耦合到GQD的信号输入的共模电平调整电路， 以及耦合到GQD和共模电平调整电路的调谐电路。 GQD评估由RC网络提供的输入信号，计算经滤波的输入信号和反馈量化信号之间的差异以产生误差信号，测量误差信号，并用Σ-Δ噪声整形补偿误差信号。 共模电平调节电路将差分输入信号的共模电平改变为基本上等于期望的共模电平，并且调谐电路基于两者之间的差异向共模电平调整电路提供补偿电压 共模级别。

公开(公告)号：US20100149013A1

公开(公告)日：2010-06-17

申请号：US12710856

申请日：2010-02-23

申请人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

发明人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

IPC分类号： H03M3/00

CPC分类号： H03M3/488

摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

公开(公告)号：US07679443B2

公开(公告)日：2010-03-16

申请号：US11729487

申请日：2007-03-29

申请人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

发明人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

IPC分类号： H03F3/45

CPC分类号： H03M3/488

摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

公开(公告)号：US07796066B2

公开(公告)日：2010-09-14

申请号：US12710856

申请日：2010-02-23

申请人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

发明人： Ayman A. Fayed ,  Russell Byrd ,  Baher Haroun

IPC分类号： H03M1/06

CPC分类号： H03M3/488

摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

摘要翻译： 用于连续时间Σ-Δ模数转换器的共模转换的系统和方法。 一个实施例包括具有耦合到差分信号输入的RC网络的环路滤波器，耦合到环路滤波器的Gm-C /量化器/ DAC电路（GQD），耦合到GQD的信号输入的共模电平调整电路， 以及耦合到GQD和共模电平调整电路的调谐电路。 GQD评估由RC网络提供的输入信号，计算经滤波的输入信号和反馈量化信号之间的差异以产生误差信号，测量误差信号，并用Σ-Δ噪声整形补偿误差信号。 共模电平调节电路将差分输入信号的共模电平改变为基本上等于期望的共模电平，并且调谐电路基于两者之间的差异向共模电平调整电路提供补偿电压 共模级别。

公开(公告)号：US07907429B2

公开(公告)日：2011-03-15

申请号：US11967714

申请日：2007-12-31

申请人： Yogesh K. Ramadass ,  Ayman A. Fayed ,  Baher Haroun

发明人： Yogesh K. Ramadass ,  Ayman A. Fayed ,  Baher Haroun

IPC分类号： H02M3/18

CPC分类号： H02M3/1584 ,  H02M3/07 ,  H02M2003/072

摘要： A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a digitally controlled transfer capacitor. A pair of non-overlapping, fixed frequency clock signals is provided to a switched capacitor circuit including the switched capacitor matrix and a load capacitor coupled to the output terminal. A DC input voltage supply is provided. A hysteretic feedback loop is used to control the voltage at the output as a stepped-down voltage from the input by digitally modulating the transfer capacitor using switches in the switch matrix to couple more, or fewer, transfer capacitors to the output terminal during a clock cycle. A coarse and a fine adjustment circuit are provided to improve the regulation during rapid changes in load power. A method of operating the regulator is disclosed.

摘要翻译： 公开了一种使用片上开关电容器提供完全集成的DC-DC转换器的电路和方法。 开关电容矩阵作为数字传输电容耦合。 一对不重叠的固定频率时钟信号被提供给包括开关电容矩阵的开关电容器电路和耦合到输出端的负载电容器。 提供一个直流输入电压源。 迟滞反馈环路用于通过使用开关矩阵中的开关对转换电容器进行数字调制来控制输出端的电压作为降压电压，以在时钟期间将更多或更少的传输电容器耦合到输出端子 周期。 提供粗调和微调电路，以改善负载功率快速变化时的调节。 公开了一种操作调节器的方法。

公开(公告)号：US20090072800A1

公开(公告)日：2009-03-19

申请号：US11967714

申请日：2007-12-31

申请人： Yogesh K. Ramadass ,  Ayman A. Fayed ,  Baher Haroun

发明人： Yogesh K. Ramadass ,  Ayman A. Fayed ,  Baher Haroun

IPC分类号： G05F1/10 ,  G05F1/00

CPC分类号： H02M3/1584 ,  H02M3/07 ,  H02M2003/072

摘要： A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a digitally controlled transfer capacitor. A pair of non-overlapping, fixed frequency clock signals is provided to a switched capacitor circuit including the switched capacitor matrix and a load capacitor coupled to the output terminal. A DC input voltage supply is provided. A hysteretic feedback loop is used to control the voltage at the output as a stepped-down voltage from the input by digitally modulating the transfer capacitor using switches in the switch matrix to couple more, or fewer, transfer capacitors to the output terminal during a clock cycle. A coarse and a fine adjustment circuit are provided to improve the regulation during rapid changes in load power. A method of operating the regulator is disclosed.

摘要翻译： 公开了一种使用片上开关电容器提供完全集成的DC-DC转换器的电路和方法。 开关电容矩阵作为数字传输电容耦合。 一对不重叠的固定频率时钟信号被提供给包括开关电容矩阵的开关电容器电路和耦合到输出端的负载电容器。 提供一个直流输入电压源。 迟滞反馈环路用于通过使用开关矩阵中的开关对转换电容器进行数字调制来控制输出端的电压作为降压电压，以在时钟期间将更多或更少的传输电容器耦合到输出端子 周期。 提供粗调和微调电路，以改善负载功率快速变化时的调节。 公开了一种操作调节器的方法。

公开(公告)号：US20100148844A1

公开(公告)日：2010-06-17

申请号：US12711035

申请日：2010-02-23

申请人： Ayman A. Fayad ,  Russell Byrd ,  Baher Haroun

发明人： Ayman A. Fayad ,  Russell Byrd ,  Baher Haroun

IPC分类号： H03L5/00

CPC分类号： H03M3/488

摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.