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公开(公告)号：US09800260B1
公开(公告)日：2017-10-24
申请号：US15343674
申请日：2016-11-04
发明人： Debopam Banerjee
CPC分类号： H03M3/412 , H03M1/124 , H03M3/452 , H03M3/454 , H03M3/458 , H03M3/488 , H04B1/0017 , H04B1/38
摘要： An apparatus comprises a delta-sigma analog-to-digital converter (ADC) and baseband processing circuitry. The delta-sigma ADC includes a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC; a main quantizer circuit including a main ADC circuit and a main digital-to-analog converter (DAC) circuit, wherein an input to the main ADC circuit is operatively coupled to the plurality of integrator stages; and a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC. The baseband circuitry is configured to activate the first feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.
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2.发明授权Method and arrangement for setting an effective resolution of an output signal in incremental delta-sigma analog-to-digital converters 有权用于在增量式Δ-Σ模数转换器中设置输出信号的有效分辨率的方法和装置公开(公告)号：US09379734B2
公开(公告)日：2016-06-28
申请号：US14939679
申请日：2015-11-12
发明人： Raik Richter , Marko Mailand
IPC分类号： H03M3/00
摘要： A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set.
摘要翻译： 用于通过增量Δ-Σ模数转换器设置增量Δ-Σ模数转换中的输出信号的有效分辨率的方法和装置包括馈送输入信号和参考电压之间的差 在第一积分器的反馈分支中形成的信号。 保护多级增量Δ-Σ模数转换器对于大输入信号范围的稳定性，不需要输入信号的直接阻尼，从而可以避免相对于ADC固有噪声源的直接SNR损害 ，通过增量Δ-Σ模数转换器的反馈支路中的虚拟参考电压来实现。 参考电压信号适应于可变参考电容的改变的输入信号范围，并且依赖于其的时钟周期数被设置。
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3.发明授权公开(公告)号：US09148169B2
公开(公告)日：2015-09-29
申请号：US14189841
申请日：2014-02-25
IPC分类号： H03M3/00
摘要： A quantizer for an analog to digital converter has an input for receiving an analog input signal. A detector senses a common mode voltage component of the input signal. A reference voltage source produces a plurality of reference voltages. A voltage source biases the reference voltage source in response to the sensed common mode voltage component. Therefore, the common mode voltage in the input signal establishes the common mode voltage of the reference voltage source. A plurality of comparators are connected to the reference voltage source, wherein each of the plurality of comparators compares the input signal to one of the plurality of reference voltages and produces a output bit denoting a result of the comparing.
摘要翻译： 用于模数转换器的量化器具有用于接收模拟输入信号的输入。 检测器检测输入信号的共模电压分量。 参考电压源产生多个参考电压。 电压源响应于感测的共模电压分量偏置参考电压源。 因此，输入信号中的共模电压建立了参考电压源的共模电压。 多个比较器连接到参考电压源，其中多个比较器中的每个比较器将输入信号与多个参考电压中的一个进行比较，并产生表示比较结果的输出位。
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公开(公告)号：US07796066B2
公开(公告)日：2010-09-14
申请号：US12710856
申请日：2010-02-23
申请人： Ayman A. Fayed , Russell Byrd , Baher Haroun
发明人： Ayman A. Fayed , Russell Byrd , Baher Haroun
IPC分类号： H03M1/06
CPC分类号： H03M3/488
摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.
摘要翻译： 用于连续时间Σ-Δ模数转换器的共模转换的系统和方法。 一个实施例包括具有耦合到差分信号输入的RC网络的环路滤波器，耦合到环路滤波器的Gm-C /量化器/ DAC电路（GQD），耦合到GQD的信号输入的共模电平调整电路， 以及耦合到GQD和共模电平调整电路的调谐电路。 GQD评估由RC网络提供的输入信号，计算经滤波的输入信号和反馈量化信号之间的差异以产生误差信号，测量误差信号，并用Σ-Δ噪声整形补偿误差信号。 共模电平调节电路将差分输入信号的共模电平改变为基本上等于期望的共模电平，并且调谐电路基于两者之间的差异向共模电平调整电路提供补偿电压 共模级别。
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5.发明申请Analog-to-digital-converter comprising a sigma-delta-modulator and receiver with such analog-to-digital-converter 审中-公开包括具有这种模数转换器的Σ-Δ调制器和接收器的模数转换器公开(公告)号：US20060164272A1
公开(公告)日：2006-07-27
申请号：US10562272
申请日：2004-06-24
IPC分类号： H03M3/00
摘要： Analog-to-digital converter including a sigma-delta modulator (SD) with noise shaping filtering. Signal transfer filtering is introduced in the feedback loop of the sigma-delta modulator. This may be done without affecting the noise shaping filtering e.g. with a signal transfer filter (L) in the forward path of the feedback loop and a complementary signal transfer path (H) in the feedback path of the loop. The analog-to-digital converter may be used for channel filtering, FM-demodulation and/or image rejection in communication receivers.
摘要翻译： 模数转换器包括具有噪声整形滤波的Σ-Δ调制器（SD）。 在Σ-Δ调制器的反馈环路中引入信号传输滤波。 这可以在不影响噪声整形滤波的情况下完成。 在反馈环路的正向路径中具有信号传输滤波器（L），并且在环路的反馈路径中具有互补信号传送路径（H）。 模数转换器可用于通信接收机中的信道滤波，FM解调和/或镜像抑制。
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6.发明授权Floating type analog-to-digital converter using delay units to achieve a wide dynamic range 失效浮动型模数转换器采用延时单元实现宽动态范围
公开(公告)号：US06104329A
公开(公告)日：2000-08-15
申请号：US98160
申请日：1998-06-16
申请人： Toshihiko Kawano
发明人： Toshihiko Kawano
CPC分类号： H03M3/488
摘要： A floating type analog-to-digital converter which is capable of converting an analog signal into a digital signal in a wide dynamic range, while exhibiting stable frequency characteristics due to the presence of symmetric pre-echo and post-echo in the impulse response waveform. An analog signal level adjusting device adjusts the level of an analog signal with different first gains, so as to generate a plurality of analog signals of different levels for analog-to-digital conversion. A plurality of analog-to-digital converters convert respective ones of the plurality of analog signals generated from the analog signal level adjusting device, into respective digital signals, and output the digital signals. A digital signal level adjusting device adjusts the levels of the digital signals with different second gains corresponding to respective inverses of the first gains, and generates the adjusted digital signals, which are then delayed and generated by a delay device. A switching device selects one of the digital signals generated from the delay device, based on the level of one digital signal selected from the digital signals generated from the plurality of analog-to-digital converters, and generates the selected one digital signal.
摘要翻译： 一种浮动型模数转换器，其能够在宽动态范围内将模拟信号转换成数字信号，同时由于在脉冲响应波形中存在对称的预回波和后回波而呈现稳定的频率特性 。 模拟信号电平调整装置利用不同的第一增益调节模拟信号的电平，以产生用于模数转换的不同电平的多个模拟信号。 多个模数转换器将从模拟信号电平调整装置产生的多个模拟信号中的各个模拟信号转换为相应的数字信号，并输出数字信号。 数字信号电平调整装置利用与第一增益的相应反转相对应的不同的第二增益来调整数字信号的电平，并产生经延迟装置延迟和产生的经调整的数字信号。 开关装置基于从从多个模数转换器产生的数字信号中选择的一个数字信号的电平，选择从延迟装置产生的一个数字信号，并产生所选择的一个数字信号。
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公开(公告)号：US20230247359A1
公开(公告)日：2023-08-03
申请号：US18298854
申请日：2023-04-11
发明人： Dietmar Straeussnigg
摘要： A digital microphone includes at least one integrator; a state detection and parameter control component directly coupled to an output of the integrator; and a signal processing component coupled to an output of the state detection and parameter control component, wherein a parameter of the signal processing component includes a first value in a first operational mode and a second value in a second operational mode different from the first operational mode.
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公开(公告)号：US20180358980A1
公开(公告)日：2018-12-13
申请号：US15616674
申请日：2017-06-07
CPC分类号： H03M3/488 , H03G3/008 , H03G3/20 , H03G3/3052 , H03G2201/307 , H03M3/492 , H04W52/0238
摘要： A scalable dynamic range analog-to-digital converter. In one instance, a method of scaling a dynamic range of an analog-to-digital converter is provided. The method includes operating the analog-to-digital converter at a first dynamic range. The method also includes receiving a radio frequency signal and detecting an on-channel signal level of the radio frequency signal. The method also includes when the on-channel signal level is above an on-channel threshold, operating the analog-to-digital converter at a second dynamic range. The method also includes when the on-channel signal level is below the on-channel threshold, operating the analog-to-digital converter at the first dynamic range.
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9.发明申请METHOD AND ARRANGEMENT FOR SETTING AN EFFECTIVE RESOLUTION OF AN OUTPUT SIGNAL IN INCREMENTAL DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS 有权用于设置输入信号在增量型三角形模拟数字转换器中的有效分辨率的方法和布置公开(公告)号：US20160142072A1
公开(公告)日：2016-05-19
申请号：US14939679
申请日：2015-11-12
发明人： Raik RICHTER , Marko MAILAND
IPC分类号： H03M3/00
摘要： A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set.
摘要翻译： 用于通过增量Δ-Σ模数转换器设置增量Δ-Σ模数转换中的输出信号的有效分辨率的方法和装置包括馈送输入信号和参考电压之间的差 在第一积分器的反馈分支中形成的信号。 保护多级增量Δ-Σ模数转换器对大输入信号范围的稳定性，不需要输入信号的直接阻尼，从而可以避免相对于ADC固有噪声源的直接SNR损害 ，通过增量Δ-Σ模数转换器的反馈支路中的虚拟参考电压来实现。 参考电压信号适应于可变参考电容的改变的输入信号范围，并且依赖于其的时钟周期数被设置。
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公开(公告)号：US20100148844A1
公开(公告)日：2010-06-17
申请号：US12711035
申请日：2010-02-23
申请人： Ayman A. Fayad , Russell Byrd , Baher Haroun
发明人： Ayman A. Fayad , Russell Byrd , Baher Haroun
IPC分类号： H03L5/00
CPC分类号： H03M3/488
摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.
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