公开(公告)号：US20130236030A1

公开(公告)日：2013-09-12

申请号：US13430701

申请日：2012-03-27

申请人： BIN-SONG MA ,  HSING-SUANG KAO

发明人： BIN-SONG MA ,  HSING-SUANG KAO

IPC分类号： H04B15/00

CPC分类号： H03K17/60 ,  H03F1/305 ,  H03G3/348 ,  H03K19/09

摘要： A mute drive circuit includes a micro-controller including an I/O port; a mute circuit; and an npn transistor. When an electronic device using the mute circuit is plugged into an AC power source, the I/O port is set to the logic low, the mute circuit performs the mute mode. When the electronic device is turned on, the I/O port is controlled set to the logic low for a period and then be pulled up to the logic high, the mute circuit performs the mute mode for the period and then enters into the normal mode. When the electronic device is turned off, the I/O port is controlled to set to the logic low, the mute circuit performs the mute mode. When the electronic device is unplugged from the AC power source, the I/O port is pulled down to the logic low, the mute circuit performs the mute mode.

摘要翻译： 静音驱动电路包括具有I / O端口的微控制器; 静音电路; 和npn晶体管。 当使用静音电路的电子设备插入交流电源时，I / O端口设置为逻辑低电平，静音电路执行静音模式。 当电子设备打开时，I / O端口被控制为逻辑低电平一段时间，然后被上拉至逻辑高电平，静音电路在该时间段内执行静音模式，然后进入正常模式 。 当电子设备关闭时，I / O端口被控制为逻辑低电平，静音电路执行静音模式。 当电子设备从交流电源拔下时，I / O端口被拉低至逻辑低电平，静音电路执行静音模式。

公开(公告)号：US20130236025A1

公开(公告)日：2013-09-12

申请号：US13430700

申请日：2012-03-27

申请人： BIN-SONG MA ,  YONG-SONG SHI

发明人： BIN-SONG MA ,  YONG-SONG SHI

IPC分类号： H04R1/10

CPC分类号： H04R3/007 ,  H03G3/348 ,  H04R3/02

摘要： An earphone jack drive circuit applied in an electronic device is provided. The earphone jack drive circuit includes a mute circuit; a micro-controller including a detect pin and a control pin; a delay switch circuit including a resistance, a capacitance, an npn transistor and a first current-limiting resistance. During the plugging in or the unplugging out of the earphone, any momentary logic high of the detect pin charges the capacitance, the capacitance discharges when the detect pin is set to be logic low. For a period, the npn transistor is kept on, the connector of the npn transistor is set to be logic low, the input port of the mute circuit is set to be logic low, thereby the mute circuit is controlled to perform the mute mode during the period to eliminate the popping noises of connection and disconnection.

摘要翻译： 提供了一种应用于电子设备中的耳机插孔驱动电路。 耳机插孔驱动电路包括静音电路; 微控制器，包括检测引脚和控制引脚; 包括电阻，电容，npn晶体管和第一限流电阻的延迟开关电路。 在插拔耳机时，检测引脚的任何瞬时逻辑高电容都会充电，当检测引脚设置为逻辑低电平时，电容放电。 在一段时间内，npn晶体管保持导通，npn晶体管的连接器设置为逻辑低电平，静音电路的输入端口设置为逻辑低电平，从而静音电路被控制为在静音模式期间执行静音模式 消除连接和断开的爆裂声音的时期。

公开(公告)号：US20130234673A1

公开(公告)日：2013-09-12

申请号：US13430702

申请日：2012-03-27

申请人： BIN-SONG MA

发明人： BIN-SONG MA

IPC分类号： H02J7/00

CPC分类号： H02J9/00

摘要： A discharge circuit for increasing discharge time of battery includes a discharging IC and a delay discharge circuit. When the discharging IC detects any voltage input, a minimum operating voltage of the discharging IC is set to 6.3V, when the discharging IC detects no voltage input, the minimum operating voltage of the discharging IC is set to 5.5 V. The delay discharge circuit is connected with a system voltage via a first current-limiting resistance, to make the discharging IC unable to detect any voltage input when only a battery is used as power source, thereby the minimum operating voltage of the discharging IC is set to 5.5V.

摘要翻译： 用于增加电池放电时间的放电电路包括放电IC和延迟放电电路。 当放电IC检测到任何电压输入时，放电IC的最小工作电压设定为6.3V，放电IC检测不到电压输入时，放电IC的最小工作电压设定为5.5V。延迟放电电路 经由第一限流电阻与系统电压连接，使得当仅使用电池作为电源时，放电IC不能检测到任何电压输入，从而将放电IC的最小工作电压设置为5.5V。