公开(公告)号：US10475409B2

公开(公告)日：2019-11-12

申请号：US15796463

申请日：2017-10-27

申请人： BOE Technology Group Co., Ltd.

发明人： Mingfu Han ,  Xing Yao ,  Guangliang Shang ,  Haoliang Zheng ,  Seung-Woo Han ,  Jiha Kim ,  Lijun Yuan ,  Zhichong Wang

IPC分类号： G11C19/00 ,  G09G3/36 ,  G06F3/041 ,  G11C19/28

摘要： The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.

公开(公告)号：US10235919B2

公开(公告)日：2019-03-19

申请号：US15577402

申请日：2017-05-03

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Guangliang Shang ,  Xing Yao ,  Mingfu Han ,  Seung-Woo Han ,  Yun-Sik Im ,  Jing Lv ,  Yinglong Huang ,  Jung-Mok Jun ,  Xue Dong ,  Haoliang Zheng ,  Lijun Yuan ,  Zhichong Wang ,  Ji Ha Kim

IPC分类号： G09G3/20 ,  G11C19/28

摘要： A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.

公开(公告)号：US20180240393A1

公开(公告)日：2018-08-23

申请号：US15712429

申请日：2017-09-22

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Hui ZHANG ,  Seung-Woo Han ,  Yun-Sik Im ,  Shunhang Zhang ,  Mingfu Han

IPC分类号： G09G3/20 ,  H01L27/12 ,  H01L29/786

CPC分类号： G09G3/2092 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0221 ,  G09G2320/0233 ,  G09G2320/0686 ,  G09G2330/021 ,  G09G2330/028 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/78636 ,  H01L29/78648

摘要： An array substrate includes a display region including at least two partitions. The array substrate includes a gate driving circuit, first gate electrodes and second gate electrodes. The gate driving circuit is configured to, while inputting a first voltage to the respective first gate electrodes for turning on corresponding thin film transistors according to normal timing, selectively input, to all the second gate electrodes in at least one of the partitions, a second voltage for turning off or turning on all thin film transistors in the partition.