Counter, pixel circuit, display panel and display device

    公开(公告)号:US11295651B2

    公开(公告)日:2022-04-05

    申请号:US16939188

    申请日:2020-07-27

    Abstract: Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.

    COUNTER, PIXEL CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE

    公开(公告)号:US20210097914A1

    公开(公告)日:2021-04-01

    申请号:US16939188

    申请日:2020-07-27

    Abstract: Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.

    Liquid crystal lens and imaging device using the same

    公开(公告)号:US11187961B2

    公开(公告)日:2021-11-30

    申请号:US16439058

    申请日:2019-06-12

    Abstract: A liquid crystal lens and an imaging device including the liquid crystal lens are provided. The liquid crystal lens includes: a first substrate and a second substrate arranged opposite to each other; a liquid crystal layer located between the first substrate and the second substrate; the liquid crystal layer is configured to transmit a first portion of incident light transmitted through the first substrate, and converge the first portion of incident light to a predetermined region of the second substrate; and a light adjustment structure arranged between the first substrate and the second substrate, and configured to enable a second portion of incident light transmitted through the first substrate to be transmitted through the liquid crystal layer and converged to the predetermined region.

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