SHIFT REGISTER, GATE DRIVING CIRCUIT, DISPLAY APPARATUS AND GATE DRIVING METHOD
    8.
    发明申请
    SHIFT REGISTER, GATE DRIVING CIRCUIT, DISPLAY APPARATUS AND GATE DRIVING METHOD 审中-公开
    移位寄存器,门驱动电路,显示装置和门驱动方法

    公开(公告)号:US20170039968A1

    公开(公告)日:2017-02-09

    申请号:US14908703

    申请日:2015-08-19

    IPC分类号: G09G3/36 G11C19/28

    摘要: The present invention provides a shift register comprising a gate driving signal generation unit, a plurality of signal output control modules, a plurality of signal output reset modules and a plurality of signal output terminals. One terminal of each signal output control module is connected with the gate driving signal generation unit and the other terminal thereof is connected with one corresponding signal output terminal, and each signal output control module also has a respective control signal input terminal for outputting the gate driving signal outputted by the gate driving signal generation unit through the corresponding signal output terminal under control of a control signal inputted from the control signal input terminal, and one terminal of each signal output reset module is connected between the corresponding signal output control module and the corresponding signal output terminal for resetting output signal of the signal output terminal connected thereto.

    摘要翻译: 本发明提供了一种移位寄存器,包括栅极驱动信号产生单元,多个信号输出控制模块,多个信号输出复位模块和多个信号输出端子。 每个信号输出控制模块的一个端子与栅极驱动信号产生单元连接,另一个端子与一个对应的信号输出端子相连,每个信号输出控制模块还具有相应的控制信号输入端,用于输出栅极驱动 在由控制信号输入端子输入的控制信号的控制下,门控驱动信号生成部通过对应的信号输出端子输出的信号,各信号输出复位模块的一端连接在对应的信号输出控制模块与相应的信号输出端 信号输出端子,用于复位与其连接的信号输出端子的输出信号。

    ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS

    公开(公告)号:US20220157857A1

    公开(公告)日:2022-05-19

    申请号:US17485136

    申请日:2021-09-24

    摘要: Disclosed are an array substrate, a display panel and a display apparatus. The array substrate includes: gate lines, data lines, and pixel units. The gate lines and the data lines are arranged between at least part of the adjacent pixel units. The array substrate further includes: common electrode lead wires and common electrode layers. The common electrode lead wires are arranged on a same layer as the data lines, extend in a same direction as the data lines, and are located between at least part of the adjacent pixel units. The common electrode layers are insulated from the common electrode lead wires through insulating layers and are connected with the common electrode lead wires through via holes in the insulating layers. The via holes are located in a region where the gate lines and the common electrode lead wires intersect.