摘要:
A random number generator includes: a random number generating circuit used for generating a pulse signal based on a control word and generating a random number signal according to the pulse signal, the pulse signal including a first frequency signal and a second frequency signal that appear alternately, and proportions of the first frequency signal and the second frequency signal being controlled by the control word; and a feedback update circuit used for updating the control word based on the random number signal output by the random number generating circuit.
摘要:
Disclosed is a resistive random access memory, comprising a substrate, an insulating layer, a bottom electrode, a resistive material film, and a top electrode in an order from bottom to top, wherein the resistive material film is a four-layer structure composed of a same metal oxide; and the four layers in the four-layer structure from bottom to top have resistance values which are increased one after another by more than 10 times, oxygen concentrations which are increased one after another and thickness which are decreased one after another. The present invention may achieve complete formation-rupture of oxygen vacancy conductive filaments (CF) in each layer by dividing the resistive material film of the same metal oxide into four layers according to the different oxygen concentrations, so as to control accurately the resistance values, so that 2-bit storage with high uniformity is achieved.
摘要:
A compute-in-memory (CIM) circuit and a control method thereof. The CIM circuit includes a memory array. The memory array comprises n1 memory blocks arranged in sequence from top to bottom, and each memory block comprises n2 rows of memory-cell rows arranged in sequence, wherein n1≥2, n2≥1. Each odd memory block and an adjacent even memory block arranged therebelow form a memory group. Each memory group comprises n2 pairs of memory-cell rows, and a k-th pair of memory-cell rows in each memory group includes a k-th memory-cell row and a (2n2+1−k)-th memory-cell row in the corresponding memory group, where 1≤k≤n2. The memory array is divided into n2 memory subarrays configured to be turned on in sequence for calculation, wherein a k-th memory subarray includes the k-th pair of memory-cell rows in each memory group.