-
公开(公告)号：US20240412707A1
公开(公告)日：2024-12-12
申请号：US18695988
申请日：2023-07-31
Inventor： Ruifang Du , Ya Yu , Haijiao Qian , Xiaoye Ma
IPC: G09G3/36
Abstract: A display baseplate includes a display region and a peripheral region, and the display baseplate includes: a substrate, and a gate line driving circuit, a plurality of signal lines, and a gate line provided on one side of the substrate, the gate line driving circuit and the plurality of signal lines all being located in the peripheral region, and the gate line being located in the display region. The gate line driving circuit is respectively connected to the plurality of signal lines and the gate line, and includes a plurality of stages of driving units that are cascaded to each other, each driving unit includes a first element group, and the first element group includes at least one first electronic element. The plurality of signal lines are arranged in a first direction, the first direction is an extending direction of the gate line.
-
公开(公告)号：US11532643B2
公开(公告)日：2022-12-20
申请号：US16096587
申请日：2018-03-12
Inventor： Binbin Cao , Yinhu Huang , Chengshao Yang , Haijiao Qian
IPC: H01L27/12 , G02F1/1362
Abstract: An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate comprises a base substrate, a plurality of gate lines and gate electrodes on the base substrate, each gate electrode being corresponding to and separate from a respective gate line, a gate insulating layer over the gate electrode and the gate line, the gate insulating layer having a first via hole and a second via hole, the first via hole exposing the gate electrode, the second via hole exposing the gate line, a conductive connection layer and a polysilicon semiconductor layer on the gate insulating layer, the conductive connection layer filling the first via hole and the second via hole to connect the gate line with the gate electrode.
-
公开(公告)号：US12113076B2
公开(公告)日：2024-10-08
申请号：US17514265
申请日：2021-10-29
Inventor： Liang Chen , Jincheng Gao , Haijiao Qian , Tao Jiang , Zexu Liu , Tao Wang , Lixing Zhao , Guanyong Zhang , Quanzhou Liu , Jiantao Liu
IPC: H01L27/12 , H01L21/311
CPC classification number: H01L27/1248 , H01L21/31116 , H01L21/31138 , H01L27/1262 , H01L27/124
Abstract: Embodiments of the disclosure provide a display substrate and a method for manufacturing the same. The display substrate includes: a base substrate; a thin film transistor including a source-drain metal layer and a first insulating layer; a second insulating layer; a color resist layer; and a third insulating layer. The third insulating layer comprises a first via hole that sequentially penetrates the third insulating layer, the color resist layer and the second insulating layer and thus extends from the third insulating layer to the source-drain metal layer. A sidewall of the first via hole comprises a first portion formed of a material of the second insulating layer, a second portion formed of a material of the color resist layer, and a third portion formed of a material of the third insulating layer, the second portion is between the first portion and the third portion.
-
公开(公告)号：US11869899B2
公开(公告)日：2024-01-09
申请号：US17357841
申请日：2021-06-24
Inventor： Ruifang Du , Lanzhou Ma , Haijiao Qian , Xiaoye Ma
CPC classification number: H01L27/124 , H01L23/60 , H01L25/18
Abstract: The present disclosure provides a GOA circuit, an array substrate and a display device, wherein the GOA circuit comprises: a GOA area, and the GOA area comprises a plurality of GOA unit circuits cascaded with each other; a lead area, wherein at least one STV signal line and at least one non-STV signal line are arranged in the lead area, each STV signal line and each non-STV signal line is connected to at least one GOA unit circuit, and the non-STV signal line comprises at least one of a Vdd signal line, a Clk signal line, a VGH signal line and a VGL signal line; a projection of the at least one STV signal line on the lead area does not overlap a projection of the at least one non-STV signal line on the lead area.
-
公开(公告)号：US20210226065A1
公开(公告)日：2021-07-22
申请号：US16099506
申请日：2017-11-22
Inventor： Binbin Cao , Haijiao Qian , Chengshao Yang , Yinhu Huang
IPC: H01L29/786 , H01L29/66
Abstract: The present application discloses a thin film transistor having an active layer including a channel part, a source contact part, and a drain contact part. At least one of the source contact part and the drain contact part has a contacting edge having one or more irregularities along the contacting edge.
-
Patent Agency Ranking
公开(公告)号：US20250123712A1
公开(公告)日：2025-04-17
申请号：US18687099
申请日：2022-12-19
Inventor： Xiaoye Ma , Ruifang Du , Haijiao Qian , Huanhuan Huang , Chengshao Yang , Ran Zhang
IPC: G06F3/041 , G02F1/13 , G02F1/1333 , G02F1/1345 , G02F1/1362 , G02F1/1368
Abstract: The present disclosure provides a liquid crystal writing board and a method for repairing the same. The liquid crystal writing board includes a first substrate, a second substrate, and a bistable liquid crystal layer disposed between the first substrate and the second substrate. The first substrate includes a plurality of first signal line groups, the first signal line group including at least two first signal lines; a plurality of second signal lines, the first signal lines and the second signal lines intersecting with each other; and a control electrode disposed in an area surrounded by two adjacent first signal lines and two adjacent second signal lines, the first signal lines and the second signal lines being configured to jointly provide control signals to the control electrode. The first signal lines in the first signal line group are electrically connected with each other.
-
公开(公告)号：US10535781B2
公开(公告)日：2020-01-14
申请号：US15988805
申请日：2018-05-24
Inventor： Lin Chen , Haijiao Qian , Chengshao Yang , Mengyu Luan
IPC: H01L29/786 , H01L29/417 , H01L29/66
Abstract: The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer.
-
公开(公告)号：US11177386B2
公开(公告)日：2021-11-16
申请号：US16099506
申请日：2017-11-22
Inventor： Binbin Cao , Haijiao Qian , Chengshao Yang , Yinhu Huang
IPC: H01L29/00 , H01L29/786 , H01L29/66
Abstract: The present application discloses a thin film transistor having an active layer including a channel part, a source contact part, and a drain contact part. At least one of the source contact part and the drain contact part has a contacting edge having one or more irregularities along the contacting edge.
-
公开(公告)号：US20210202537A1
公开(公告)日：2021-07-01
申请号：US16074976
申请日：2017-11-14
Inventor： Binbin Cao , Haijiao Qian , Chengshao Yang , Yinhu Huang
IPC: H01L27/12
Abstract: A manufacturing method of an array substrate, an array substrate and a display device are disclosed. The manufacturing method of the array substrate includes: providing a base substrate (200); forming a semiconductor layer on the base substrate; depositing an etch stop layer material on the semiconductor layer; subjecting the etch stop layer material to a wet etching process to form an etch stop layer; subjecting the semiconductor layer to a dry etching process to form an active layer, wherein the active layer includes a first region and a second region surrounding the first region, an orthographic projection of the etch stop layer on the base substrate completely coincides with an orthographic projection of the first region of the active layer on the base substrate.
-
10.发明授权公开(公告)号：US10923597B2
公开(公告)日：2021-02-16
申请号：US16427730
申请日：2019-05-31
Inventor： Haijiao Qian , Chengshao Yang , Yinhu Huang , Yunhai Wan
IPC: H01L29/786 , H01L27/12 , H01L29/45 , H01L29/66
Abstract: A transistor and a method for manufacturing the same, a display substrate, and a display apparatus are provided. The transistor may include: a substrate; an active region on the substrate and including a polycrystalline silicon region; an etch stop layer at a side of the polycrystalline silicon region distal to the substrate; and a first heavily doped amorphous silicon region and a second heavily doped amorphous silicon region both at a side of the etch stop layer distal to the substrate; the polycrystalline silicon region having a first side surface corresponding to the first heavily doped amorphous silicon region and a second side surface corresponding to the second heavily doped amorphous silicon region; wherein an orthographic projection of the polycrystalline silicon region on a plane in which a lower surface of the etch stop layer lies does not go beyond the lower surface of the etch stop layer.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.014 seconds)
