COMPACT LOW-POWER FULLY DIGITAL CMOS CLOCK GENERATION APPARATUS FOR HIGH-SPEED SERDES
    1.
    发明申请
    COMPACT LOW-POWER FULLY DIGITAL CMOS CLOCK GENERATION APPARATUS FOR HIGH-SPEED SERDES 有权
    针对高速串口的紧凑型低功耗全数字CMOS时钟发生器

    公开(公告)号:US20150180649A1

    公开(公告)日:2015-06-25

    申请号:US14637306

    申请日:2015-03-03

    CPC classification number: H04L7/0331 H03L7/00 H03L7/0996 H04L7/0016

    Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

    Abstract translation: 高速时钟发生器装置包括相位插值器(PI)电路,平滑块和基于反相器的低通滤波器。 PI电路接收具有不同相位角的多个时钟信号,并产生具有正确相位角的输出时钟信号。 平滑块平滑具有不同相位角的时钟信号,并产生多个具有改进线性度的平滑时钟信号。 基于逆变器的低通滤波器滤波具有不同相位角的时钟信号的谐波。

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