公开(公告)号：US20150381150A1

公开(公告)日：2015-12-31

申请号：US14336979

申请日：2014-07-21

Applicant: BROADCOM CORPORATION

Inventor： Afshin MOMTAZ ,  Adesh GARG

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K19/017545 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0282

Abstract: An apparatus for driving a load using a low supply voltage includes a voltage-mode driver and a current source arrangement. The voltage-mode driver provides a desired termination impedance and a first portion of a desired output current to the load. The current source arrangement provides a second portion of the desired output current. The desired output current generates a predetermined voltage swing across the load, while the voltage-mode driver and the current source arrangement are powered by the low supply voltage.

Abstract translation: 使用低电源电压驱动负载的装置包括电压模式驱动器和电流源装置。 电压模式驱动器提供期望的终端阻抗和期望的输出电流的第一部分到负载。 电流源装置提供期望输出电流的第二部分。 期望的输出电流在负载上产生预定的电压摆幅，而电压模式驱动器和电流源装置由低电源电压供电。

公开(公告)号：US20150180649A1

公开(公告)日：2015-06-25

申请号：US14637306

申请日：2015-03-03

Applicant: BROADCOM CORPORATION

Inventor： Mahmoud Reza AHMADI ,  Siavash FALLAHI ,  Tamer ALI ,  Ali NAZEMI ,  Hassan MAAREFI ,  Burak CATLI ,  Afshin MOMTAZ

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  H03L7/00 ,  H03L7/0996 ,  H04L7/0016

Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Abstract translation: 高速时钟发生器装置包括相位插值器（PI）电路，平滑块和基于反相器的低通滤波器。 PI电路接收具有不同相位角的多个时钟信号，并产生具有正确相位角的输出时钟信号。 平滑块平滑具有不同相位角的时钟信号，并产生多个具有改进线性度的平滑时钟信号。 基于逆变器的低通滤波器滤波具有不同相位角的时钟信号的谐波。

公开(公告)号：US20140079169A1

公开(公告)日：2014-03-20

申请号：US14080733

申请日：2013-11-14

Applicant: Broadcom Corporation

Inventor： Bharath RAGHAVAN ,  Jun CAO ,  Afshin MOMTAZ

IPC: H03K5/07 ,  H04L7/02

CPC classification number: H03K5/07 ,  H03K2005/00071 ,  H03K2005/00208 ,  H03M9/00 ,  H04L7/0079 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033

Abstract: A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.

Abstract translation: 可编程频率接收机包括用于以第一频率接收数据的分片器，用于以第二频率解复用数据的解复用器，用于产生第一频率的时钟的可编程时钟发生器，以及第一和第二谐振时钟放大器 用于在第一和第二频率处放大时钟信号。 谐振时钟放大器包括具有低Q值的电感器，允许它们在接收器的可编程频率范围上放大时钟信号。 第二谐振时钟放大器包括数字可调谐延迟元件，以在限幅器和解复用器之间的接口处在数据窗口中延迟和居中放大的第二频率的时钟信号。 延迟元件可以是电容器。 校准电路调整主时钟发生器内的电容元件，以产生第一个频率的主时钟。