公开(公告)号：US09853615B2

公开(公告)日：2017-12-26

申请号：US15139030

申请日：2016-04-26

Applicant: BROADCOM CORPORATION

Inventor： Md Shakil Akter ,  Klaas Bult

IPC: H03F3/45 ,  H03M1/12 ,  H03F1/02 ,  H03G3/30 ,  H03F1/34 ,  H03G1/00

CPC classification number: H03F3/45179 ,  H03F1/3211 ,  H03F1/34 ,  H03F3/45 ,  H03F3/45071 ,  H03F3/45085 ,  H03F3/45183 ,  H03F2200/294 ,  H03F2200/297 ,  H03F2200/372 ,  H03F2200/489 ,  H03G1/0029 ,  H03G1/0052 ,  H03G3/3015 ,  H03M1/0695 ,  H03M1/124 ,  H03M1/164

Abstract: A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

公开(公告)号：US20170302237A1

公开(公告)日：2017-10-19

申请号：US15139030

申请日：2016-04-26

Applicant: BROADCOM CORPORATION

Inventor： Md Shakil Akter ,  Klaas Bult

IPC: H03F3/45 ,  H03F1/02 ,  H03M1/12

CPC classification number: H03F3/45179 ,  H03F1/3211 ,  H03F1/34 ,  H03F3/45 ,  H03F3/45071 ,  H03F3/45085 ,  H03F3/45183 ,  H03F2200/294 ,  H03F2200/297 ,  H03F2200/372 ,  H03F2200/489 ,  H03G1/0029 ,  H03G1/0052 ,  H03G3/3015 ,  H03M1/0695 ,  H03M1/124 ,  H03M1/164

Abstract: A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).