公开(公告)号：US3610903A

公开(公告)日：1971-10-05

申请号：US3610903D

申请日：1969-01-08

Applicant: BURROUGHS CORP

Inventor： STOKES RICHARD A ,  TYGER VERNON H JR ,  DAVIS ROBERT L ,  FABER ULBE

IPC: G06F5/01 ,  G06F5/00

CPC classification number: G06F5/015

Abstract: The disclosure of the present invention describes an electronic shift network, termed a barrel switch, which is comprised of a matrix of gates arranged in a rectangular configuration and adapted to shift in a single clock time a multibit parallel input a preselected number of places to the left or right, either endoff or end-around. The controls for operating the barrel switch are also described in detail.

公开(公告)号：US3878514A

公开(公告)日：1975-04-15

申请号：US30786372

申请日：1972-11-20

Applicant: BURROUGHS CORP

Inventor： FABER ULBE

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F15/78 ,  G06F9/16

CPC classification number: G06F15/7832 ,  G06F9/226 ,  G06F9/265

Abstract: A microprogrammable serial byte processor suitable for complete implementation of memory, logic, control and addressing functions on a single integrated circuit chip through large scale integration technology. An instruction set, at the microprogrammable level, is provided for controlling the processor in executing basic computer functions. Each instruction of the instruction set has a unique format which is decoded and executed by a circuit design that initially represents minimally committed logic or hardware, and which becomes committed to a specific task by control signals which are decoded from the formatted instructions. Specific circuitry for executing serially by bit the individual instructions of the instruction set is maintained at a simple and minimal level by employing a soft mechine architecture with a microprogramming approach.

Abstract translation: 适用于通过大规模集成技术在单个集成电路芯片上完全实现存储器，逻辑，控制和寻址功能的可编程串行字节处理器。 提供了可编程级的指令集，用于控制处理器执行基本的计算机功能。 指令集的每个指令具有唯一的格式，其通过最初表示最低限度提交的逻辑或硬件的电路设计来解码和执行，并且由从格式化指令解码的控制信号变为致力于特定任务。 通过采用具有微程序方法的软机械结构，用于串行地执行指令集的各个指令的特定电路被保持在简单和最小的水平。

公开(公告)号：US3651473A

公开(公告)日：1972-03-21

申请号：US3651473D

申请日：1970-03-27

Applicant: BURROUGHS CORP

Inventor： FABER ULBE

IPC: G06F13/40 ,  G06F15/16 ,  G06F15/26

CPC classification number: G06F13/4022

Abstract: This disclosure relates to an expandable interlocking exchange for a multiprocessing system that allows additional processors, memory modules and peripheral devices to be coupled to the exchange without incurring signal degradation and increased noise during data transfer. The exchange is a cross matrix of inputoutput buses or ports, for each of the accessing units, and interconnecting buses. Expansion is achieved by removing one of the accessing units from the exchange and employing the gates, which coupled that unit to the exchange, to couple the interconnecting buses to a new set of interconnecting buses to service the additional units.

Abstract translation: 本公开涉及一种用于多处理系统的可扩展互锁交换机，其允许附加处理器，存储器模块和外围设备耦合到交换机，而不会在数据传输期间引起信号劣化和增加的噪声。 交换机是对于每个访问单元和互连总线的输入 - 输出总线或端口的交叉矩阵。 通过从交换机中移除一个访问单元并使用将该单元耦合到交换机的门来将互连总线耦合到一组新的互连总线来服务附加单元来实现扩展。

公开(公告)号：US3629857A

公开(公告)日：1971-12-21

申请号：US3629857D

申请日：1969-09-18

Applicant: BURROUGHS CORP

Inventor： FABER ULBE

IPC: G06F7/78 ,  G06F9/26 ,  G11C7/00

CPC classification number: G06F7/785 ,  G06F9/264

Abstract: This disclosure relates to a memory or storage array that can be accessed randomly and also in both a first in-first out mode and a first in-last out mode. The array is word oriented and each word location is provided with an indicator flip-flop which is placed in a ONE state when a word has been entered therein, the flip-flop being reset to ZERO when the word has been fetched from that location in a nonrandom access mode. Address logic is provided to select the next successive location in one of the fetching modes having the same sequence as the storage mode. In addition, the address logic provides for selecting locations in an opposite sequence and for selecting locations in a random manner during the other fetching modes.