公开(公告)号：US4326247A

公开(公告)日：1982-04-20

申请号：US946222

申请日：1978-09-25

申请人： George P. Chamberlin

发明人： George P. Chamberlin

IPC分类号： G06F9/48 ,  G06F9/16

CPC分类号： G06F9/4825

摘要： A data processor having an internal address bus and a separate internal data bus which are selectively coupled to an external memory bus. The external memory bus is time shared so that it can carry memory addresses as well as data. A command shift register, at least one capture register, a timer register, a compare register, a control register, and a status register are all coupled to the internal data bus. The command shift register is capable of serially shifting data, upon command, to an output terminal. The at least one capture register is capable of being loaded from the timer register whenever a transition occurs on a predetermined input to the data processor thereby capturing the time at which the transition occurred. The compare register is used to store a digital signal equivalent to some desired time. The compare register is continuously compared for equality with the timer register and provides a signal when equality exists. The control register is capable of providing software control of preselected registers within the data processor and the status register is used to temporarily store data indicating causes of interrupts.

摘要翻译： 具有内部地址总线和分离的内部数据总线的数据处理器，其选择性地耦合到外部存储器总线。 外部存储器总线是时间共享的，因此它可以携带存储器地址以及数据。 命令移位寄存器，至少一个捕捉寄存器，定时器寄存器，比较寄存器，控制寄存器和状态寄存器都被耦合到内部数据总线。 命令移位寄存器能够根据命令将数据串行移位到输出端子。 只要在对数据处理器的预定输入发生转换，从而捕获发生转换的时间，至少一个捕获寄存器能够从定时器寄存器加载。 比较寄存器用于存储等同于一些所需时间的数字信号。 连续比较寄存器与定时器寄存器相等，并在等于存在时提供信号。 控制寄存器能够提供对数据处理器内的预选寄存器的软件控制，状态寄存器用于临时存储指示中断原因的数据。

公开(公告)号：US4225920A

公开(公告)日：1980-09-30

申请号：US941193

申请日：1978-09-11

申请人： Richard A. Stokes

发明人： Richard A. Stokes

IPC分类号： G06F9/28 ,  G06F9/38 ,  G06F9/16 ,  G06F13/00

CPC分类号： G06F9/28 ,  G06F9/38

摘要： In a microprogrammed data processing pipeline system comprising a plurality of stages, microinstructions for controlling the stages are stored as templates in an addressable template micromemory store and are provided automatically and sequentially to the stages of the pipeline system. Operation microcode is introduced for a particular stage after the templates are issued from the micromemory store but before provision thereof to the pipeline system, thereby allowing a single template to control a plurality of different operations of a particular stage within the pipeline system. Provision is also made to freeze or inhibit the issuance of subsequent templates during the execution of excessively long operations in the particular stage.

摘要翻译： 在包括多个级的微程序数据处理流水线系统中，用于控制级的微指令作为模板存储在可寻址模板微存储器中，并且被自动且顺序地提供给管线系统的级。 在从微存储器存储模板之后，但在将其提供给流水线系统之前，为特定阶段引入操作微代码，从而允许单个模板来控制流水线系统内的特定级的多个不同操作。 还规定在特定阶段执行过长的业务期间，冻结或禁止后续模板的发行。

公开(公告)号：US4212074A

公开(公告)日：1980-07-08

申请号：US927938

申请日：1978-07-25

申请人： Shiro Kuno ,  Yoshiharu Nishimura

发明人： Shiro Kuno ,  Yoshiharu Nishimura

IPC分类号： G01G23/365 ,  G01G19/414 ,  G01G23/16 ,  G01G23/37 ,  G06F17/40 ,  G06F9/16 ,  G01G7/00 ,  G06F15/20

CPC分类号： G01G23/3707

摘要： A weight measuring apparatus comprises a load cell for generating an analog signal corresponding to load applied, and A/D converter for converting an output signal from the load cell into a digital signal, a data processing unit which periodically reads a digital output signal out from the A/D converter to successively write the digital output signal into a first memory area of the memory and produces data corresponding to the weight of load applied to the load cell on the basis of plurality of digital data stored in the first memory area of the memory to write the data into a second memory area of the memory, and a display unit for displaying the data from the data processing unit.The data processing unit compares a plurality of digital data stored in the first memory area. As a result of the comparison, when a given number of or more digital data having the same values are included in the digital data stored in the first memory area, the digital data is produced as output data. On the other hand, when the digital data having the same values fail to reach the given number, the digital data stored in the second memory area and the latest or newest one of the digital data read out from the A/D converter are compared. When the difference between the two compared digital data exceeds a given value, the latest digital data is produced as output data. When, on the other hand, the difference is less than the given value, the data stored in the second memory area is read out and outputted.

摘要翻译： 一种重量测量装置，包括用于产生对应于所施加的负载的模拟信号的测力传感器，以及用于将来自测力传感器的输出信号转换为数字信号的A / D转换器，周期性地读取数字输出信号的数据处理单元 所述A / D转换器将所述数字输出信号连续地写入所述存储器的第一存储器区域，并且基于存储在所述存储器的所述第一存储器区域中的多个数字数据产生与施加到所述负载单元的负载的权重相对应的数据 用于将数据写入存储器的第二存储区域的存储器，以及用于显示来自数据处理单元的数据的显示单元。 数据处理单元比较存储在第一存储区域中的多个数字数据。 作为比较的结果，当存储在第一存储区域中的数字数据中包括具有相同值的给定数量的数字数据被包括在数字数据中时，产生数字数据作为输出数据。 另一方面，当具有相同值的数字数据不能达到给定数量时，比较存储在第二存储区域中的数字数据和从A / D转换器读出的最新或最新的数字数据。 当两个比较的数字数据之间的差异超过给定值时，产生最新的数字数据作为输出数据。 另一方面，当差值小于给定值时，存储在第二存储区域中的数据被读出并输出。

公开(公告)号：US4209847A

公开(公告)日：1980-06-24

申请号：US909647

申请日：1978-05-25

申请人： Shigeo Noda ,  Hideo Honma ,  Sadamu Kato

发明人： Shigeo Noda ,  Hideo Honma ,  Sadamu Kato

IPC分类号： B23Q15/00 ,  G05B19/4093 ,  G05B19/414 ,  G05B19/4155 ,  G05B19/42 ,  G06F15/46 ,  G06F9/16

CPC分类号： G05B19/4202 ,  G05B19/414 ,  G05B2219/36031 ,  G05B2219/36243 ,  G05B2219/36283

摘要： A computerized numerical controller wherein a tape reader, upon reading of input tapes, inputs machine control data including source language instruction data into a storage device of a data processing device. The processing device, when operated under the control of an automatic programming program, converts the source language instruction data into blocks of machine part instruction data and stores the same in the storage device. The processing device, when operated under the control of a numerical control program, produces command signals each indicative of the length and velocity that a machine apparatus connected thereto is to move, in accordance with each of the blocks of the machine part instruction data and outputs the command signals to the machine apparatus so as to control the same. The processing device is enabled to operate selectively under the above-mentioned two programs.

摘要翻译： 一种计算机化数字控制器，其中磁带阅读器在读取输入磁带时，将包括源语言指令数据的机器控制数据输入到数据处理设备的存储设备中。 处理装置在自动编程程序的控制下操作时，将源语言指令数据转换为机器部分指令数据块，并将其存储在存储装置中。 处理装置在数字控制程序的控制下操作时，根据机器部分指令数据和输出的每个块产生指示与其连接的机器装置移动的长度和速度的指令信号 该命令发信号给机器设备以便控制它。 处理装置能够在上述两个程序下有选择地运行。

公开(公告)号：US4124890A

公开(公告)日：1978-11-07

申请号：US808119

申请日：1977-06-20

申请人： Alexandr A. Vasenkov ,  Valery L. Dshkhunian ,  Pavel R. Mashevich ,  Petr V. Nesterov ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin ,  Davlet I. Juditsky

发明人： Alexandr A. Vasenkov ,  Valery L. Dshkhunian ,  Pavel R. Mashevich ,  Petr V. Nesterov ,  Vyacheslav V. Telenkov ,  Jury E. Chicherin ,  Davlet I. Juditsky

IPC分类号： G06F9/28 ,  G06F9/16 ,  G06F15/16

CPC分类号： G06F9/28

摘要： According to the invention, a microprocessor computing system comprises at least one data processing device and at least one group of execution control elements; said group constitutes a control level and includes at least one microprogram control device which is a group of first-order control elements. The data processing device incorporates a microinstruction register for holding microinstruction codes, a microoperation decoder, a general-purpose register unit for holding operands, an arithmetic/logic unit, a temporary result storage register, a result status register, and at least one data exchange unit having a multichannel communication line to provide for data exchange between other sources and destinations. The microprogram control device producing parallel microinstruction codes incorporates at least one input register, a programmable address unit, a microinstruction storage unit, a feedback register, a microinstruction register, and an output driver unit.Each data processing device and each microprogram control device as well, comprise an internal operating cycle generator to generate clock signals of the internal operating cycle, which are used to control data sequencing in the related device, all said internal operating cycle generators being linked through at least one clock signal bus.

摘要翻译： 根据本发明，微处理器计算系统包括至少一个数据处理装置和至少一组执行控制元件; 所述组构成控制级，并且包括至少一个微程序控制装置，其是一组一级控制元件。 数据处理装置包括用于保存微指令代码的微指令寄存器，微操作解码器，用于保存操作数的通用寄存器单元，算术/逻辑单元，临时结果存储寄存器，结果状态寄存器和至少一个数据交换 单元具有多通道通信线路以提供其他源和目的地之间的数据交换。 产生并行微指令代码的微程序控制装置包括至少一个输入寄存器，可编程地址单元，微指令存储单元，反馈寄存器，微指令寄存器和输出驱动器单元。

公开(公告)号：US4104720A

公开(公告)日：1978-08-01

申请号：US745898

申请日：1976-11-29

申请人： Ronald Hans Gruner

发明人： Ronald Hans Gruner

IPC分类号： G06F9/22 ,  G06F9/28 ,  G06F9/38 ,  G06F9/46 ,  G06F15/16 ,  G06F15/80 ,  G06F9/16

CPC分类号： G06F15/8015

摘要： There is disclosed a data processing system which employs parallel processors (PP's or P--P's) that are interfaced to the CPU, and which derive their control from microinstructions stored in an extension to the CPU microcode structure. This extension forms part of the CPU/PP interface. The P--P's increase speed of operation of the data processing system in which they are employed by operating synchronously and simultaneously with the CPU when called upon by CPU microcode structure to execute particular algorithms.

摘要翻译： 公开了一种数据处理系统，其采用与CPU接口的并行处理器（PP或P-P），并从存储在CPU微代码结构的扩展中的微指令导出其控制。 此扩展构成了CPU / PP接口的一部分。 通过CPU微代码结构调用执行特定算法时，P-P通过与CPU同步运行并同步地提高数据处理系统的运行速度。

公开(公告)号：US4099229A

公开(公告)日：1978-07-04

申请号：US768445

申请日：1977-02-14

申请人： H. Clifford Kancler

发明人： H. Clifford Kancler

IPC分类号： G06F9/30 ,  G06F9/16 ,  G06F1/00 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F9/30149

摘要： A variable architecture digital computer to provide real-time control comations a for missile by executing efficient variable-length instructions optimized for such application by means of a microprogrammed processor and an instruction byte string concept.

摘要翻译： 一种可变架构数字计算机，通过执行通过微程序处理器和指令字节串概念为这种应用而优化的有效的可变长度指令，为导弹提供实时控制计算。

公开(公告)号：US4091451A

公开(公告)日：1978-05-23

申请号：US791113

申请日：1977-04-26

申请人： Peter D. Weiner ,  Charles W. Calhoun ,  Jerry A. Collins ,  Gary Lynn Mee

发明人： Peter D. Weiner ,  Charles W. Calhoun ,  Jerry A. Collins ,  Gary Lynn Mee

IPC分类号： B25B23/151 ,  B23P19/06 ,  B25B23/14 ,  E21B19/16 ,  G01L5/24 ,  G06F9/16

CPC分类号： E21B19/166 ,  B23P19/06 ,  B23P19/066 ,  B25B23/14

摘要： A method of and apparatus for making up two members having mating threaded connections, such as pipe joints or bolts, for insuring that a specified number of threads have been engaged and a specific torque has been applied. The mating threaded connections are threadably engaged while measurements are made of the torque required to turn one of the members relative to the other, and measurements are made of the number of turns of the members relative to each other. In order to insure that a bad joint is not made up, the measurements of torque and turns must remain within specified parameters or the threaded interconnection is discontinued. The method and apparatus further includes avoiding erroneous turn measurements that may occur such as due to bending or swaying of one of the members during makeup.

摘要翻译： 一种用于制造具有配合螺纹连接件的两个构件的方法和装置，例如管接头或螺栓，用于确保已经接合了指定数量的螺纹并且施加了特定的扭矩。 匹配的螺纹连接件是螺纹接合的，同时测量成形件相对于另一个转动所需的扭矩，并且测量构件相对于彼此的匝数。 为了确保没有组合坏接头，扭矩和转动的测量值必须保持在指定的参数内，或螺纹互连中断。 所述方法和装置还包括避免可能发生的错误的转弯测量，例如由于在化妆过程中其中一个构件的弯曲或摇动。

公开(公告)号：US4087857A

公开(公告)日：1978-05-02

申请号：US729066

申请日：1976-10-04

申请人： Thomas F. Joyce ,  Michel M. Raguin

发明人： Thomas F. Joyce ,  Michel M. Raguin

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/16

CPC分类号： G06F9/268

摘要： A method and an apparatus for improving the speed of executing instructions and reducing the microprogram memory requirements in a conventional digital computer system by eliminating a ROM address register for addressing microwords. The method or apparatus incorporates the use of a predetermined bit position in the microinstruction word which is set to a binary one when the microword is the last microword of an executing microprogram. The apparatus is responsive to the electronic representation of the binary one signal to cause the microinstruction execution sequence to branch to a predetermined location in the microprogram memory for execution of the following microinstruction; thus eliminating one ROM address register and at least one step in returning to a common address for starting the execution of another microprogram.

摘要翻译： 一种用于通过消除用于寻址微词的ROM地址寄存器来提高传统数字计算机系统中执行指令的速度并降低微程序存储器要求的方法和装置。 该方法或装置包括在微指令字中使用预定位位置，当微字是执行微程序的最后一个微时字时，微指令字被设置为二进制位。 该装置响应于二进制一个信号的电子表示，以使微指令执行序列分支到微程序存储器中的预定位置，以执行以下微指令; 从而消除一个ROM地址寄存器和至少一个步骤返回到用于开始执行另一个微程序的公共地址。

公开(公告)号：US4073005A

公开(公告)日：1978-02-07

申请号：US435356

申请日：1974-01-21

申请人： Thomas R. Parkin

发明人： Thomas R. Parkin

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F9/18 ,  G06F9/16 ,  G06F13/08

CPC分类号： G06F9/4881

摘要： Two or more processors share a large main memory in which are stored the programs and data sets on which the processors operate. Each processor operates independently from every other one, and selects its tasks for operation on the basis of information contained in tables which may be updated independently by each processor.

摘要翻译： 两个或多个处理器共享一个大的主存储器，其中存储处理器所处的程序和数据集。 每个处理器独立于其他处理器操作，并且基于可由每个处理器独立更新的表中包含的信息来选择其操作任务。