LDPC (low density parity check) code size adjustment by shortening and puncturing

    公开(公告)号:US08473817B2

    公开(公告)日:2013-06-25

    申请号:US12632552

    申请日:2009-12-07

    IPC分类号: H03M13/35

    摘要: LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.

    LDPC (low density parity check) codes with corresponding parity check matrices selectively constructed with CSI (cyclic shifted identity) and null sub-matrices
    2.
    发明授权
    LDPC (low density parity check) codes with corresponding parity check matrices selectively constructed with CSI (cyclic shifted identity) and null sub-matrices 有权
    具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码

    公开(公告)号:US08370731B2

    公开(公告)日:2013-02-05

    申请号:US13423381

    申请日:2012-03-19

    IPC分类号: G06F11/10

    摘要: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

    摘要翻译: 具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成,并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI(循环移位身份)子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上,另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵(即,其中的所有元素是0的值)。

    Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder
    3.
    发明申请
    Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder 有权
    重叠的基于子矩阵的LDPC(低密度奇偶校验)解码器

    公开(公告)号:US20100138721A1

    公开(公告)日:2010-06-03

    申请号:US12651453

    申请日:2010-01-01

    IPC分类号: H03M13/29 G06F11/10 H03M13/05

    摘要: Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

    摘要翻译: 重叠的基于子矩阵的LDPC(低密度奇偶校验)解码器。 提出了新的解码方法,通过该方法,立即采用对应于LDPC矩阵的子矩阵的更新的位边消息来更新与该子矩阵相对应的校验边消息,而不需要存储位边消息; 立即采用对应于LDPC矩阵的子矩阵的更新的校验边消息来更新与该子矩阵相对应的位边消息,而不需要存储校验边消息。 与执行整个LDPC矩阵的所有校验边消息的更新的系统相比,使用这种方法,在给定时间段内可以执行两倍的解码迭代,然后更新整个LDPC矩阵的所有位边消息,以及 所以。 当结合最小和处理执行这种重叠方法时,也可以节省大量的内存。

    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices
    4.
    发明申请
    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices 失效
    具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码

    公开(公告)号:US20090327847A1

    公开(公告)日:2009-12-31

    申请号:US12533306

    申请日:2009-07-31

    IPC分类号: G06F11/10

    摘要: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

    摘要翻译: 具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成,并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI(循环移位身份)子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上,另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵(即,其中的所有元素为零“0”)。

    FIXED-SPACING PARITY INSERTION FOR FEC (FORWARD ERROR CORRECTION) CODEWORDS
    5.
    发明申请
    FIXED-SPACING PARITY INSERTION FOR FEC (FORWARD ERROR CORRECTION) CODEWORDS 有权
    用于FEC(前向纠错)编码的固定间隔奇偶校验插入

    公开(公告)号:US20090193312A1

    公开(公告)日:2009-07-30

    申请号:US12021911

    申请日:2008-01-29

    IPC分类号: H04L1/18

    摘要: Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities.

    摘要翻译: 用于FEC(前向纠错)码字的固定间隔奇偶校验插入。 当产生码字时,使用固定间隔来分散信息比特之间的奇偶比特。 根据该固定间隔,在码字中的每个奇偶校验位之间放置相同数量的信息比特。 如果需要,奇偶校验位的顺序可以在它们被置入码字之前改变。 此外,信息比特的顺序也可以在它们被置入码字之前被修改。 用于从信息比特生成奇偶校验位的FEC编码可以是各种代码中的任何一种,包括里德 - 所罗门(RS)码,LDPC(低密度奇偶校验)码,turbo码,turbo格状编码调制(TTCM) 或提供FEC能力的一些其他代码。

    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices
    6.
    发明授权
    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices 有权
    具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码

    公开(公告)号:US08631312B2

    公开(公告)日:2014-01-14

    申请号:US13753579

    申请日:2013-01-30

    IPC分类号: H03M13/00

    摘要: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

    摘要翻译: 具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成,并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI(循环移位身份)子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上,另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵(即,其中的所有元素为零“0”)。

    LDPC (low density parity check) code size adjustment by shortening and puncturing
    9.
    发明授权
    LDPC (low density parity check) code size adjustment by shortening and puncturing 失效
    通过缩短和穿孔对LDPC(低密度奇偶校验)码大小进行调整

    公开(公告)号:US07631246B2

    公开(公告)日:2009-12-08

    申请号:US11417316

    申请日:2006-05-03

    IPC分类号: H03M13/35

    摘要: LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.

    摘要翻译: LDPC(低密度奇偶校验)码字大小调整通过缩短和删截。 可以使用选择的缩短和删截从初始LDPC码生成各种LDPC编码信号。 使用LDPC码大小调整方法,硬件设计能够处理原始LDPC码的单个通信设备也能够在进行适当的缩短和删截之后处理由原始LDPC码构成的各种其他LDPC码。 这提供了重要的设计简化和复杂性的降低,因为可以实现相同的硬件以适应从原始LDPC码产生的各种LDPC码。 因此,可以实现能够处理几个所生成的LDPC码的具有多LDPC码的通信装置。 这种方法允许在LDPC码设计中具有极大的灵活性,因为可以在执行缩短和删截之后维持原始码率。

    Implementation of LDPC (low density parity check) decoder by sweeping through sub-matrices
    10.
    发明授权
    Implementation of LDPC (low density parity check) decoder by sweeping through sub-matrices 失效
    通过扫描子矩阵来实现LDPC(低密度奇偶校验)解码器

    公开(公告)号:US07617433B2

    公开(公告)日:2009-11-10

    申请号:US11360268

    申请日:2006-02-23

    IPC分类号: H03M13/00

    摘要: Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1st columns in 1 or more sub-matrices, all 2nd columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1st rows in 1 or more sub-matrices, all 2nd rows in 1 or more sub-matrices, etc.).

    摘要翻译: 通过扫描子矩阵实现LDPC(低密度奇偶校验)解码器。 提出了一种解码处理与LDPC码对应的低密度奇偶校验矩阵的各个子矩阵的列和行的LDPC编码信号的新方法。 低密度奇偶校验矩阵可以根据它的每个子矩阵划分成行和列,并且这些子矩阵中的每一个也包括相应的行和列。 例如,当执行位节点处理时,可以一起处理1个或更多个子矩阵的相同列(例如,1个或更多个子矩阵中的所有第1列,1个或更多个子矩阵中的所有第2列等 。)。 类似地,当执行校验节点处理时,可以一起处理1个或更多个子矩阵的相同行(例如,1个或更多个子矩阵中的所有第1行,1个或更多个子矩阵中的所有第2行等) 。