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公开(公告)号：US07082584B2
公开(公告)日：2006-07-25
申请号：US10427609
申请日：2003-04-30
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.
摘要翻译： 一种自动分析RTL代码的方法包括接收集成电路设计的输入RTL代码。 选择了一种集成电路设计供应商的设计规则的RTL平台。 设计规则从图形用户界面的RTL平台显示。 从图形用户界面中选择了多个设计规则。 在RTL代码的RTL平台中对每个选定的设计规则进行分析。 生成分析结果作为每个选定设计规则的输出。
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公开(公告)号：US06907588B2
公开(公告)日：2005-06-14
申请号：US10334743
申请日：2002-12-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method of estimating congestion for register transfer level code includes steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor plan, computing routing demand numbers for the regions in the floor plan, computing routing resource numbers for the regions in the floor plan, and generating a congestion estimate of the register transfer level code as a function of the routing demand numbers and the routing resource numbers.
摘要翻译： 估计寄存器传送级代码的拥塞的方法包括以下步骤：接收作为输入的从寄存器传送级代码映射的平面图，识别平面图中的区域，计算平面图中的区域的路由需求数，计算路由资源号 对于平面图中的区域，并且根据路由需求号码和路由资源号码生成寄存器传送级别代码的拥塞估计。
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公开(公告)号：US06757885B1
公开(公告)日：2004-06-29
申请号：US10334570
申请日：2002-12-31
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method of generating a length matrix for register transfer level code includes steps for receiving as input register transfer level code, an I/O block list, a plurality of compile units, and a user defined hierarchical depth; mapping the register transfer level code to a design library, generating a connectivity matrix for the plurality of compile units, generating a priority list of interconnections from the connectivity matrix, generating placement coordinates for the compile units from the priority list of interconnections and the connectivity matrix, and generating as output at least one of the connectivity matrix and the placement coordinates.
摘要翻译： 一种生成用于寄存器传送级代码的长度矩阵的方法，包括用于接收作为输入寄存器传送级代码，I / O块列表，多个编译单元和用户定义的分层深度的步骤; 将所述寄存器传送级代码映射到设计库，生成所述多个编译单元的连接矩阵，从所述连接矩阵生成互连优先级列表，从所述互连优先级列表生成所述编译单元的布局坐标以及所述连接矩阵 并且产生作为连接矩阵和放置坐标中的至少一个的输出。
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4.发明申请Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database 审中-公开用于分析集成电路设计的方法和计算机程序，以使用设计闭包知识库和物理设计数据库来识别和解决以多规则违规为特征的有问题的结构公开(公告)号：US20070079266A1
公开(公告)日：2007-04-05
申请号：US11241033
申请日：2005-09-30
申请人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
发明人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and computer program product analyzes an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations uses a Design Closure Knowledge Base to generate a corrective action strategy in a Design Closure Guidance Report. In one embodiment, a method includes steps of receiving as input an integrated circuit design and a set of design rules, analyzing the integrated circuit design to identify design rule violations, and generating as output a compilation of each of the design rule violations and a corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations. The compilation of each of the design rule violations and the corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations is included in a Design Closure Knowledge Base to generate a detailed and structured strategy for resolving the design rule violations in the Design Closure Guidance Report.
摘要翻译： 一种方法和计算机程序产品分析集成电路设计，以识别和解决以多规则违规为特征的有问题的结构，使用设计闭合知识库在“设计闭合指导报告”中生成纠正措施策略。 在一个实施例中，一种方法包括以下步骤：接收集成电路设计和一组设计规则作为输入，分析集成电路设计以识别设计规则违反，以及生成作为输出的每个设计规则违规的汇编以及对应的 集成电路设计中的每个设计规则违规的主要和次要对象列表。 每个设计规则违规的汇编以及每个设计规则违规的集成电路设计中的主要和次要对象的相应列表都包含在设计闭包知识库中，以生成详细和结构化的解决设计规则的策略 违反设计关闭指引报告。
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5.发明授权Advanced design format library for integrated circuit design synthesis and floorplanning tools 失效高级设计格式库集成电路设计综合和布局规划工具公开(公告)号：US06990651B2
公开(公告)日：2006-01-24
申请号：US10438530
申请日：2003-05-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An integrated circuit design library includes a timing parameter representative of a design element in an integrated circuit; an area size parameter representative of the design element in an integrated circuit; and a routing demand parameter representative of a number of connections required for the design element for each value of the timing parameter and the area size parameter.
摘要翻译： 集成电路设计库包括代表集成电路中的设计元件的定时参数; 表示集成电路中的设计元素的面积大小参数; 以及路线需求参数，其表示针对定时参数和面积大小参数的每个值的设计元素所需的连接数。
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6.发明申请Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design 失效集成电路设计中同步和异步时钟域交叉管理的方法和计算机程序公开(公告)号：US20050273741A1
公开(公告)日：2005-12-08
申请号：US10859874
申请日：2004-06-02
CPC分类号： G06F17/5045 , G06F1/12
摘要： A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path between synchronous clock domains is defined as a false path in the integrated circuit design, then reporting a fatal violation.
摘要翻译： 公开了一种用于管理同步和异步时钟域交叉的方法和计算机程序，其包括以下步骤：（a）作为输入接收集成电路设计; （b）识别集成电路设计中的同步时钟域和异步时钟域之间的路径之间的路径; 和（c）如果在集成电路设计中将同步时钟域之间的路径定义为虚路径，则报告致命违规。
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7.发明授权Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design 失效集成电路设计中同步和异步时钟域交叉管理的方法和计算机程序公开(公告)号：US07412678B2
公开(公告)日：2008-08-12
申请号：US10859874
申请日：2004-06-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F1/12
摘要： A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path between synchronous clock domains is defined as a false path in the integrated circuit design, then reporting a fatal violation.
摘要翻译： 公开了一种用于管理同步和异步时钟域交叉的方法和计算机程序，其包括以下步骤：（a）作为输入接收集成电路设计; （b）识别集成电路设计中的同步时钟域和异步时钟域之间的路径之间的路径; 和（c）如果在集成电路设计中将同步时钟域之间的路径定义为虚路径，则报告致命违规。
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