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公开(公告)号：US20090282307A1
公开(公告)日：2009-11-12
申请号：US12117381
申请日：2008-05-08
CPC分类号： G01R31/31835 , G01R31/318314
摘要： A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.
摘要翻译： 公开了一种优化测试代码生成的方法。 该方法通常包括以下步骤：（A）从数据库（i）读取多个断言，（ii）测试台和（iii）所有被测设计的目标代码覆盖，（B）一起生成（i） 多个第一测试向量来测试断言，以及（ii）可应用于测试台的多个第二测试向量，（C）识别第一测试向量与第二测试向量之间的一个或多个冗余测试向量集，以及（D） 生成测试代码以使用第一测试向量和第二测试向量的子集在测试台上测试被测设计，该子集包括冗余测试向量集的单个实例。
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公开(公告)号：US20090063564A1
公开(公告)日：2009-03-05
申请号：US11849391
申请日：2007-09-04
IPC分类号： G06F17/30
CPC分类号： G06F17/5022 , G06F2217/10
摘要： A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.
摘要翻译： 公开了统计设计关闭的方法。 该方法通常包括以下步骤：（A）从数据库读取统计数据，统计数据定义多个芯片产量改进，分别在多个设计闭合类别中的每一个中的芯片产量改进之一，芯片产量改进 （B）基于统计数据计算当前设计关闭项目的多个目标，分别在每个设计关闭类别中的目标之一和（C）生成一个 向用户显示指示预期用于当前设计关闭项目的多个资源的资源报告。
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公开(公告)号：US20100217564A1
公开(公告)日：2010-08-26
申请号：US12393358
申请日：2009-02-26
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5031
摘要： A method of physical simulation of an integrated circuit design comprising the steps of (A) reading design information for an integrated circuit from a computer readable storage medium, (B) reading library information and physical design information from the computer readable storage medium, (C) simulating the integrated circuit design based upon the library information and the physical design information using a computer, where the simulation of the integrated circuit design provides signoff accurate results and (D) determining whether the integrated circuit design meets one or more performance goals based upon results of the simulation of the integrated circuit design.
摘要翻译： 一种集成电路设计的物理模拟方法，包括以下步骤：（A）从计算机可读存储介质读取集成电路的设计信息，（B）从计算机可读存储介质读取库信息和物理设计信息，（C ）基于库信息和使用计算机的物理设计信息来模拟集成电路设计，其中集成电路设计的仿真提供了签约准确的结果，以及（D）确定集成电路设计是否满足一个或多个基于 集成电路设计仿真结果。
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4.发明授权Method and computer program for incremental placement and routing with nested shells 失效方法和计算机程序，用于带嵌套外壳的增量放置和路由公开(公告)号：US07415687B2
公开(公告)日：2008-08-19
申请号：US11244530
申请日：2005-10-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and routing of the integrated circuit design is analyzed to find a critical location and is partitioned into a series of nested shells. Each shell surrounds the critical location and each preceding shell. An ordering of the shells and at least one of a timing constraint and an area constraint are selected for each shell. Each shell is placed and routed in the order selected according to the timing constraint and area constraint.
摘要翻译： 放置和布线集成电路设计的方法包括为集成电路设计的至少一部分生成初始放置和布线。 分析集成电路设计的初始放置和路由，以找到关键位置，并将其分成一系列嵌套的shell。 每个外壳围绕关键位置和每个前面的外壳。 为每个shell选择shell的排序和时序约束和面积约束中的至少一个。 每个外壳按照时序约束和面积限制选择的顺序放置和布线。
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5.发明申请Method and computer program for incremental placement and routing with nested shells 失效方法和计算机程序，用于带嵌套外壳的增量放置和路由公开(公告)号：US20070079273A1
公开(公告)日：2007-04-05
申请号：US11244530
申请日：2005-10-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method of placing and routing an integrated circuit design includes steps of (a) generating an initial placement and routing for at least a portion of an integrated circuit design; (b) analyzing the initial placement and routing of the integrated circuit design to find a critical location; (c) partitioning the initial placement and routing of the integrated circuit design into a series of nested shells wherein each shell surrounds the critical location and each preceding shell; (d) selecting an ordering of the shells; (e) selecting at least one of a timing constraint and an area constraint for each shell; and (f) placing and routing each shell in the order selected in step (d) according to the at least one timing constraint and area constraint selected in step (e).
摘要翻译： 放置和布线集成电路设计的方法包括以下步骤：（a）为集成电路设计的至少一部分生成初始放置和布线; （b）分析集成电路设计的初始放置和路由以找到关键位置; （c）将集成电路设计的初始放置和布线划分成一系列嵌套的壳体，其中每个壳体围绕关键位置和每个先前的壳体; （d）选择炮弹的命令; （e）为每个壳体选择时序约束和面积约束中的至少一个; 以及（f）根据在步骤（e）中选择的至少一个定时约束和区域约束，以步骤（d）中选择的顺序放置和布置每个外壳。
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6.发明申请Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database 审中-公开用于分析集成电路设计的方法和计算机程序，以使用设计闭包知识库和物理设计数据库来识别和解决以多规则违规为特征的有问题的结构公开(公告)号：US20070079266A1
公开(公告)日：2007-04-05
申请号：US11241033
申请日：2005-09-30
申请人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
发明人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and computer program product analyzes an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations uses a Design Closure Knowledge Base to generate a corrective action strategy in a Design Closure Guidance Report. In one embodiment, a method includes steps of receiving as input an integrated circuit design and a set of design rules, analyzing the integrated circuit design to identify design rule violations, and generating as output a compilation of each of the design rule violations and a corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations. The compilation of each of the design rule violations and the corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations is included in a Design Closure Knowledge Base to generate a detailed and structured strategy for resolving the design rule violations in the Design Closure Guidance Report.
摘要翻译： 一种方法和计算机程序产品分析集成电路设计，以识别和解决以多规则违规为特征的有问题的结构，使用设计闭合知识库在“设计闭合指导报告”中生成纠正措施策略。 在一个实施例中，一种方法包括以下步骤：接收集成电路设计和一组设计规则作为输入，分析集成电路设计以识别设计规则违反，以及生成作为输出的每个设计规则违规的汇编以及对应的 集成电路设计中的每个设计规则违规的主要和次要对象列表。 每个设计规则违规的汇编以及每个设计规则违规的集成电路设计中的主要和次要对象的相应列表都包含在设计闭包知识库中，以生成详细和结构化的解决设计规则的策略 违反设计关闭指引报告。
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公开(公告)号：US08001497B2
公开(公告)日：2011-08-16
申请号：US12243768
申请日：2008-10-01
CPC分类号： G06F17/505 , G06F2217/84
摘要： Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block.
摘要翻译： 公开了一种复制控制信号源的方法，包括：接收功能块的描述，该功能块包括多个多路复用器结构，多个存储块和至少一个复用器结构的组合中的至少一个，并且至少 一个记忆块 识别控制所述多个多路复用器结构，所述多个存储器块中的至少一个以及至少一个复用器结构和至少一个存储器块的所述组合的控制信号; 并且，确定第一副本控制信号和第二复制控制信号，所述第一副本控制信号和所述第二副本控制信号共同起到所述控制信号的作用，以控制所述多个多路复用器结构中的至少一个，所述多个存储器 块，以及所述至少一个复用器结构和至少一个存储器块的组合。
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公开(公告)号：US20070083839A1
公开(公告)日：2007-04-12
申请号：US11247630
申请日：2005-10-11
CPC分类号： G06F17/5045
摘要： A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in the file while the designer is editing the code to generate a plurality of characterization results and (C) generating a plurality of suggestions to the designer to modify the code based on a comparison of a plurality of goals for the circuit design and the characterization results.
摘要翻译： 公开了一种开发电路设计的方法。 该方法通常包括以下步骤：（A）基于从设计者接收的多个编辑来编辑用于电路设计的文件，该文件包含用硬件描述语言编写的代码，（B）表征文件中的代码，同时 设计人员正在编辑代码以生成多个表征结果;（C）基于对于电路设计和表征结果的多个目标的比较，向设计者生成多个建议以修改代码。
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公开(公告)号：US06907588B2
公开(公告)日：2005-06-14
申请号：US10334743
申请日：2002-12-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method of estimating congestion for register transfer level code includes steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor plan, computing routing demand numbers for the regions in the floor plan, computing routing resource numbers for the regions in the floor plan, and generating a congestion estimate of the register transfer level code as a function of the routing demand numbers and the routing resource numbers.
摘要翻译： 估计寄存器传送级代码的拥塞的方法包括以下步骤：接收作为输入的从寄存器传送级代码映射的平面图，识别平面图中的区域，计算平面图中的区域的路由需求数，计算路由资源号 对于平面图中的区域，并且根据路由需求号码和路由资源号码生成寄存器传送级别代码的拥塞估计。
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公开(公告)号：US06757885B1
公开(公告)日：2004-06-29
申请号：US10334570
申请日：2002-12-31
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method of generating a length matrix for register transfer level code includes steps for receiving as input register transfer level code, an I/O block list, a plurality of compile units, and a user defined hierarchical depth; mapping the register transfer level code to a design library, generating a connectivity matrix for the plurality of compile units, generating a priority list of interconnections from the connectivity matrix, generating placement coordinates for the compile units from the priority list of interconnections and the connectivity matrix, and generating as output at least one of the connectivity matrix and the placement coordinates.
摘要翻译： 一种生成用于寄存器传送级代码的长度矩阵的方法，包括用于接收作为输入寄存器传送级代码，I / O块列表，多个编译单元和用户定义的分层深度的步骤; 将所述寄存器传送级代码映射到设计库，生成所述多个编译单元的连接矩阵，从所述连接矩阵生成互连优先级列表，从所述互连优先级列表生成所述编译单元的布局坐标以及所述连接矩阵 并且产生作为连接矩阵和放置坐标中的至少一个的输出。
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