公开(公告)号：US4567641A

公开(公告)日：1986-02-04

申请号：US650314

申请日：1984-09-12

申请人： Bantval J. Baliga ,  Peter V. Gray ,  Robert P. Love

发明人： Bantval J. Baliga ,  Peter V. Gray ,  Robert P. Love

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/331 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78 ,  H01L21/441 ,  H01L21/465

CPC分类号： H01L21/30608 ,  H01L21/308 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/41766 ,  H01L29/4975

摘要： An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method of fabricating a MOSFET, an N.sup.+ SOURCE is diffused into a P BASE through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N.sup.+ SOURCE through the same window. The etchant removes most of the N.sup.+ SOURCE, but allows shoulders thereof to remain intact. These shoulders, which form the completed N.sup.+ SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method.

摘要翻译： 公开了一种具有减小长度的扩散区域的改进的半导体器件和制造这种半导体器件的改进方法。 作为示例，半导体器件可以是MOSFET或IGR。 以制造MOSFET的方法的形式，N + SOURCE通过扩散掩模的窗口扩散到P BASE中。 各向异性或定向蚀刻剂通过相同的窗口施加到N + SOURCE。 蚀刻剂除去大部分N + SOURCE，但允许其肩部保持完整。 构成完成的N + SOURCE区域的这些肩部的长度减小，大大降低了MOSFET中寄生双极晶体管导通的风险。 当通过改进的方法制造IGR时，IGR中的寄生双极晶体管的导通的风险也同样降低。

公开(公告)号：US4571815A

公开(公告)日：1986-02-25

申请号：US650315

申请日：1984-09-12

申请人： Bantval J. Baliga ,  Robert P. Love

发明人： Bantval J. Baliga ,  Robert P. Love

IPC分类号： H01L21/332 ,  H01L21/335 ,  H01L21/74 ,  H01L29/10 ,  H01L21/38

CPC分类号： H01L29/66363 ,  H01L21/743 ,  H01L29/1066 ,  H01L29/66416

摘要： A vertical channel junction gate electric field controlled device (e.g., a field effect transistor or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves on the upper surface of the base region layer but not extending to the grooves are upper electrode regions, for example, source electrode regions or cathode electrode regions. Formed in the groove bottoms and sidewalls are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions at the bottoms of the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection. The structure facilitates fabrication by methods, also disclosed, which avoid any critical photolithographic alignment steps in masking to define the locations of the source (or cathode) and gate regions, and avoid the need for any mask or mask alignment for metal definition when forming electrode metallization. As a result of the structure of the upper electrode and gate regions, it is not critical to avoid any metal deposition on the groove sidewalls.

摘要翻译： 垂直沟道结栅电场控制装置（例如，场效应晶体管或场控晶闸管）包括半导体基区域层和形成在基区域层的上表面中的具有垂直壁的多个沟槽。 在基底区域层的上表面上的凹槽之间但不延伸到沟槽的是上电极区域，例如源电极区域或阴极电极区域。 形成在凹槽底部和侧壁中的是结栅区域。 上电极端子金属化通常在上部器件层上蒸发，并且栅极端子金属化在沟槽底部的结栅区域之上。 因此，所公开的结构沿着用于低电阻栅极连接的凹入栅极区域具有连续的金属化。 该结构有利于通过还公开的方法制造，其避免了掩模中限定源极（或阴极）和栅极区域的位置的任何关键的光刻对准步骤，并且避免了在形成电极时需要用于金属界定的任何掩模或掩模对准 金属化。 作为上电极和栅极区域的结构的结果，避免在槽侧壁上的任何金属沉积是关键的。

公开(公告)号：US4516143A

公开(公告)日：1985-05-07

申请号：US579229

申请日：1984-02-13

申请人： Robert P. Love

发明人： Robert P. Love

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/41725 ,  H01L29/7802 ,  H01L29/41766 ,  H01L29/42376

摘要： Double diffused power MOSFET's and methods of manufacture. The source, base and drain regions of a double diffused power MOSFET correspond respectively to the emitter, base and collector of a parasitic bipolar transistor. Double diffused power MOSFET's perform better when provided with an ohmic short between the source and base regions to prevent turn-on of the parasitic bipolar transistor. In one form of ohmic short between the base and source regions, the source terminal comprises a metallic electrode, preferably aluminum, deposited over the source region, and the ohmic short comprises at least one microalloy spike extending from the source terminal metallic electrode through the source region and partly into the base region. Such microalloy spikes are formed by heating the semiconductor substrate after the metallic electrode has been deposited under appropriate conditions. In another form, a V-groove is formed by preferential etching in the source and base regions. In particular the V-groove extends through the source region, with the bottom of the V-groove extending only partly into the base region. A metallic source electrode is deposited over the source region and into the V-groove in ohmic contact with both the source and base regions to form both the source terminal and the ohmic short. These two forms of ohmic short are integral in nature, and facilitate an overall MOSFET structure and manufacturing process characterized by a minimum number of masking steps, self-alignment, and increased active device area.

摘要翻译： 双扩散功率MOSFET及其制造方法。 双扩散功率MOSFET的源极，基极和漏极区分别对应于寄生双极晶体管的发射极，基极和集电极。 当在源极和基极区之间提供欧姆短路时，双扩散功率MOSFET的性能更好，以防止寄生双极晶体管的导通。 在基极和源极区之间的欧姆短路的一种形式中，源极端子包括沉积在源极区上的金属电极，优选为铝，欧姆短包括从源极端子金属电极延伸通过源极的至少一个微合金尖峰 区域，部分进入基地区。 这种微合金尖峰是在金属电极在合适的条件下沉积之后加热半导体衬底形成的。 在另一种形式中，通过在源极和基极区域中的优先蚀刻形成V形槽。 特别地，V形槽延伸穿过源区域，V形槽的底部仅部分地延伸到基部区域中。 金属源电极沉积在源极区域上并进入V沟槽，与源极和基极区域欧姆接触，以形成源极端子和欧姆短路。 这两种形式的欧姆短路器本质上是一体的，并且促进了整体MOSFET结构和制造工艺，其特征在于最少数量的掩模步骤，自对准和增加的有源器件面积。

公开(公告)号：US4598461A

公开(公告)日：1986-07-08

申请号：US693643

申请日：1985-01-22

申请人： Robert P. Love

发明人： Robert P. Love

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/40

CPC分类号： H01L29/7802 ,  H01L29/41766 ,  H01L29/42376

摘要： Double diffused power MOSFET's and methods of manufacture. The source, base and drain regions of a double diffused power MOSFET correspond respectively to the emitter, base and collector of a parasitic bipolar transistor. Double diffused power MOSFET's perform better when provided with an ohmic short between the source and base regions to prevent turn-on of the parasitic bipolar transistor. In one form of ohmic short between the base and source regions, the source terminal comprises a metallic electrode, preferably aluminum, deposited over the source region, and the ohmic short comprises at least one microalloy spike extending from the source terminal metallic electrode through the source region and partly into the base region. Such microalloy spikes are formed by heating the semiconductor substrate after the metallic electrode has been deposited under appropriate conditions. In another form, a V-groove is formed by preferential etching in the source and base regions. In particular the V-groove extends through the source region, with the bottom of the V-groove extending only partly into the base region. A metallic source electrode is deposited over the source region and into the V-groove in ohmic contact with both the source and base regions to form both the source terminal and the ohmic short. These two forms of ohmic short are integral in nature, and facilitate an overall MOSFET structure and manufacturing process characterized by a minimum number of masking steps, self-alignment, and increased active device area.

摘要翻译： 双扩散功率MOSFET及其制造方法。 双扩散功率MOSFET的源极，基极和漏极区分别对应于寄生双极晶体管的发射极，基极和集电极。 当在源极和基极区之间提供欧姆短路时，双扩散功率MOSFET的性能更好，以防止寄生双极晶体管的导通。 在基极和源极区之间的欧姆短路的一种形式中，源极端子包括沉积在源极区上的金属电极，优选为铝，欧姆短包括从源极端子金属电极延伸穿过源极的至少一个微合金尖峰 区域，部分进入基地区。 这种微合金尖峰是在金属电极在合适的条件下沉积之后加热半导体衬底形成的。 在另一种形式中，通过在源极和基极区域中的优先蚀刻形成V形槽。 特别地，V形槽延伸穿过源区域，V形槽的底部仅部分地延伸到基部区域中。 金属源电极沉积在源极区域上并进入V沟槽，与源极和基极区域欧姆接触，以形成源极端子和欧姆短路。 这两种形式的欧姆短路器本质上是一体的，并且促进了整体MOSFET结构和制造工艺，其特征在于最少数量的掩模步骤，自对准和增加的有源器件面积。