公开(公告)号：US20220398367A1

公开(公告)日：2022-12-15

申请号：US17840163

申请日：2022-06-14

申请人： Battelle Memorial Institute

发明人： Katie T. Liszewski ,  Timothy A. McDonley

IPC分类号： G06F30/33

摘要： The present disclosure provides a satisfiability modulo theory (SMT) modeling system that includes graphical representation circuitry to generate graphical data representing a circuit design; finite state machine (FSM) discovery circuitry to discover, based on a feedback loop of the circuit design, an FSM contained within the graphical data; SMT assertion generation circuitry to generate an SMT assertion set of the FSM, based on the combinatorial and/or sequential logic elements associated with the FSM; and SMT modeling circuitry to determine a behavior of the FSM by applying one or more logical functions to the SMT assertion set.

公开(公告)号：US20230044517A1

公开(公告)日：2023-02-09

申请号：US17817904

申请日：2022-08-05

申请人： Battelle Memorial Institute

发明人： Timothy A. McDonley ,  Andrew Elliott ,  Adam Kimura ,  Katie T. Liszewski ,  Thomas Kent ,  Josh Delozier ,  Benjamin Hayden

IPC分类号： G06F30/327 ,  G06F30/337

摘要： The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.