公开(公告)号：US20220188491A1

公开(公告)日：2022-06-16

申请号：US17545572

申请日：2021-12-08

申请人： Battelle Memorial Institute

发明人： Adam Kimura ,  Rohan Prabhu ,  Noah Mun

IPC分类号： G06F30/327 ,  G06F30/333 ,  G06F30/392 ,  G06N3/08

摘要： In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.

公开(公告)号：US20230044517A1

公开(公告)日：2023-02-09

申请号：US17817904

申请日：2022-08-05

申请人： Battelle Memorial Institute

发明人： Timothy A. McDonley ,  Andrew Elliott ,  Adam Kimura ,  Katie T. Liszewski ,  Thomas Kent ,  Josh Delozier ,  Benjamin Hayden

IPC分类号： G06F30/327 ,  G06F30/337

摘要： The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.

公开(公告)号：US20240249050A1

公开(公告)日：2024-07-25

申请号：US18408018

申请日：2024-01-09

申请人： Battelle Memorial Institute

发明人： Adam Kimura ,  Rohan Prabhu ,  Noah Mun

IPC分类号： G06F30/327 ,  G06F30/27 ,  G06F30/3308 ,  G06F30/333 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06F119/18 ,  G06N3/08

CPC分类号： G06F30/327 ,  G06F30/333 ,  G06F30/392 ,  G06N3/08 ,  G06F30/27 ,  G06F30/3308 ,  G06F30/367 ,  G06F30/398 ,  G06F2119/18

摘要： In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.

公开(公告)号：US20240169512A1

公开(公告)日：2024-05-23

申请号：US17988850

申请日：2022-11-17

申请人： Battelle Memorial Institute

发明人： Adam Kimura ,  Vince A. McKinsey ,  Adam R. Waite

IPC分类号： G06T7/00

CPC分类号： G06T7/001 ,  G06T2200/24 ,  G06T2207/10061 ,  G06T2207/30148

摘要： In an integrated circuit (IC) analysis, a reference IC layout is stored. Instructions are readable and executable by an electronic processor to perform an IC analysis method, including: receiving layer images of a physical IC; extracting polygons depicted in the layer images; detecting errors in the physical IC by applying homeomorphic error detection to compare the extracted polygons with polygons of the reference IC layout; and displaying the detected errors on the display. The detecting of errors may include detecting an error comprising a topological inequivalence between an extracted polygon or pair of polygons and a polygon or pair of polygons of the reference IC layout. The detecting of errors may include detecting an error comprising a topological coverage error.

公开(公告)号：US11907627B2

公开(公告)日：2024-02-20

申请号：US17545572

申请日：2021-12-08

申请人： Battelle Memorial Institute

发明人： Adam Kimura ,  Rohan Prabhu ,  Noah Mun

IPC分类号： G06F30/327 ,  G06F30/392 ,  G06F30/333 ,  G06F30/27 ,  G06F30/3308 ,  G06F30/367 ,  G06F30/398 ,  G06N3/08 ,  G06F119/18

CPC分类号： G06F30/327 ,  G06F30/333 ,  G06F30/392 ,  G06N3/08 ,  G06F30/27 ,  G06F30/3308 ,  G06F30/367 ,  G06F30/398 ,  G06F2119/18

摘要： In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.