公开(公告)号：US20120066483A1

公开(公告)日：2012-03-15

申请号：US12882434

申请日：2010-09-15

申请人： Bechara F. Boury ,  Michael Bryan Mitchell ,  Paul Michael Steinmetz ,  Kenichi Tsuchiya

发明人： Bechara F. Boury ,  Michael Bryan Mitchell ,  Paul Michael Steinmetz ,  Kenichi Tsuchiya

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F12/0875 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889

摘要： A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.

摘要翻译： 计算设备包括：指令高速缓存，以顺序的顺序存储主执行单元指令和辅助执行单元指令; 主执行单元，被配置为从指令高速缓存接收和执行主执行单元指令; 辅助执行单元，被配置为以与主执行单元无关并且与异步的方式从指令高速缓存接收并执行辅助执行单元指令; 以及完成电路，其被配置为根据顺序顺序来协调主执行单元和辅助执行单元指令执行主执行单元指令的完成。

公开(公告)号：US09201801B2

公开(公告)日：2015-12-01

申请号：US12882434

申请日：2010-09-15

申请人： Bechara F. Boury ,  Michael Bryan Mitchell ,  Paul Michael Steinmetz ,  Kenichi Tsuchiya

发明人： Bechara F. Boury ,  Michael Bryan Mitchell ,  Paul Michael Steinmetz ,  Kenichi Tsuchiya

IPC分类号： G06F9/30 ,  G06F12/08 ,  G06F9/38

CPC分类号： G06F12/0875 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889

摘要： A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.

摘要翻译： 计算设备包括：指令高速缓存，以顺序的顺序存储主执行单元指令和辅助执行单元指令; 主执行单元，被配置为从指令高速缓存接收和执行主执行单元指令; 辅助执行单元，被配置为以与主执行单元无关并且与异步的方式从指令高速缓存接收并执行辅助执行单元指令; 以及完成电路，其被配置为根据顺序顺序来协调主执行单元和辅助执行单元指令执行主执行单元指令的完成。

公开(公告)号：US07752396B2

公开(公告)日：2010-07-06

申请号：US12196705

申请日：2008-08-22

申请人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

发明人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0833

摘要： Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

摘要翻译： 实施例包括高速缓存控制器，其适于确定处理器将要发出仅地址杀死请求的存储器线是否驻留在共享状态下的高速缓存行的填充缓冲器中。 如果是这样，高速缓存控制器可以将填充缓冲区标记为没有完成总线事务并且发出针对该填充缓冲区的仅地址杀死请求。 只有地址的中断请求可以发送到总线上的其他处理器，而其他处理器可以通过使存储器线的高速缓存条目无效来进行响应。 在其他处理器确认之后，总线仲裁器可以确认杀死请求，将已经在该填充缓冲器中的存储器线路推送到独占状态。 一旦被提升，填充缓冲器可以被标记为完成总线事务并且可以被写入高速缓存。

公开(公告)号：US07523265B2

公开(公告)日：2009-04-21

申请号：US11083615

申请日：2005-03-18

申请人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

发明人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0833

摘要： Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

摘要翻译： 考虑了在缓存中促进从共享到独占的系统和布置。 实施例包括高速缓存控制器，其适于确定处理器将要发出仅地址杀死请求的存储器线是否驻留在共享状态下的高速缓存行的填充缓冲器中。 如果是这样，高速缓存控制器可以将填充缓冲区标记为没有完成总线事务并且发出针对该填充缓冲区的仅地址杀死请求。 只有地址的中断请求可以发送到总线上的其他处理器，而其他处理器可以通过使存储器线的高速缓存条目无效来进行响应。 在其他处理器确认之后，总线仲裁器可以确认杀死请求，将已经在该填充缓冲器中的存储器线路推送到独占状态。 一旦被提升，填充缓冲器可以被标记为完成总线事务并且可以被写入高速缓存。

公开(公告)号：US20080313410A1

公开(公告)日：2008-12-18

申请号：US12196705

申请日：2008-08-22

申请人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

发明人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

IPC分类号： G06F12/08

CPC分类号： G06F12/0833

摘要： Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

摘要翻译： 实施例包括高速缓存控制器，其适于确定处理器将要发出仅地址杀死请求的存储器线是否驻留在共享状态下的高速缓存行的填充缓冲器中。 如果是这样，高速缓存控制器可以将填充缓冲区标记为没有完成总线事务并且发出针对该填充缓冲区的仅地址杀死请求。 只有地址的中断请求可以发送到总线上的其他处理器，而其他处理器可以通过使存储器线的高速缓存条目无效来进行响应。 在其他处理器确认之后，总线仲裁器可以确认杀死请求，将已经在该填充缓冲器中的存储器线路推送到独占状态。 一旦被提升，填充缓冲器可以被标记为完成总线事务并且可以被写入高速缓存。