SUPERCONDUCTING QUANTUM CHIP
    1.
    发明公开

    公开(公告)号:US20230195988A1

    公开(公告)日:2023-06-22

    申请号:US18108585

    申请日:2023-02-11

    Inventor: Kehui YU Lijing Jin

    CPC classification number: G06F30/39 G06N10/00

    Abstract: A method is provided. The method includes: obtaining a parameter value of a determined dimension parameter, an initial parameter value of a dimension parameter to be optimized, and a target capacitance value of an interdigital capacitor; partitioning a geometric structure of the interdigital capacitor to obtain a plurality of sections of the interdigital capacitor, where the plurality of sections are in a one-to-one correspondence with a plurality of coplanar multiple-transmission line models; obtaining a capacitance value expression of the interdigital capacitor based on the plurality of coplanar multiple-transmission line models; determining, based on the parameter value of the determined dimension parameter, the target capacitance value, and the capacitance value expression of the interdigital capacitor, a loss function including the dimension parameter to be optimized; and optimizing, based on the initial parameter value by minimizing the loss function, the parameter value of the dimension parameter to be optimized.

    QUANTUM CHIP AND CONSTRUCTION METHOD AND CONSTRUCTION APPARATUS THEREOF

    公开(公告)号:US20230172076A1

    公开(公告)日:2023-06-01

    申请号:US18095994

    申请日:2023-01-11

    CPC classification number: H10N60/12 G06N10/40 H10N60/805

    Abstract: A quantum chip is provided, includes: a first substrate and a second substrate arranged opposite to each other, wherein a plurality of qubits and a plurality of first controllers are arranged on a surface of the first substrate facing the second substrate, each of the plurality of qubits is coupled with at least one of the plurality of first controllers, and a plurality of control signal transmission parts are arranged on a surface of the second substrate facing the first substrate; and a plurality of connecting pieces, connected between the first substrate and the second substrate, and configured to connect the plurality of first controllers to the plurality of control signal transmission parts in a one-to-one corresponding mode.

    QUANTUM CHIP STRUCTURE, DETERMINING METHOD, DEVICE AND STORAGE MEDIUM

    公开(公告)号:US20230325700A1

    公开(公告)日:2023-10-12

    申请号:US17983163

    申请日:2022-11-08

    CPC classification number: G06N10/40 H03K17/92

    Abstract: Provided are a quantum chip structure, a determining method, a device and a storage medium, and relates to the field of computer technology, and in particular, to the field of quantum computation. The quantum chip structure includes: a ring structure composed of n center qubits, where two adjacent center qubits in the ring structure are connected through a coupler; and n is a natural number greater than or equal to 3; and two-linear structures drawn from a center qubit Qi toward outside of the ring structure; where a first linear structure in the two-linear structures contains ai first qubits; and a second linear structure in the two-linear structures contains bi second qubits. In this way, a quantum chip structure with high connectivity is obtained.

    METHOD AND APPARATUS FOR COUPLING SUPERCONDUCTING QUBIT, ELECTRONIC DEVICE, COMPUTER MEDIUM

    公开(公告)号:US20240061986A1

    公开(公告)日:2024-02-22

    申请号:US18386528

    申请日:2023-11-02

    CPC classification number: G06F30/392 G06N10/40

    Abstract: The present disclosure provides a method and apparatus for coupling a superconducting qubit. The method includes: determining a target coupling strength between a target read cavity and a qubit, a first target frequency of the qubit, and a second target frequency of the target read cavity; initializing a read coupling port configuration layout based on a configuration of the qubit, a relative position of the qubit to the target read cavity; calculating a to-be-measured coupling strength between the qubit and the read coupling port, based on the read coupling port configuration layout, the first target frequency, and the second target frequency; and in response to detecting that the to-be-measured coupling strength and the target coupling strength satisfy a preset condition, generating, based on the second target frequency and the read coupling port configuration layout, a complete layout comprising the qubit and the target read cavity.

    PULSE-BASED QUANTUM GATE IMPLEMENTATION

    公开(公告)号:US20230087100A1

    公开(公告)日:2023-03-23

    申请号:US17943982

    申请日:2022-09-13

    Abstract: A method is provided. The method includes determining a corresponding relationship between a pulse enveloping parameter and a single pulse duration, and determining a parameter to be optimized; and determining a maximum pulse number, an initialized current pulse number and a preset error tolerance. The method further includes executing an iterative operation including determining a quantum gate matrix to be implemented and a value of a loss function based on the current pulse number and the parameter to be optimized; adjusting a group of parameter values of the parameter to be optimized to minimize the value of the loss function; determining an error with a target quantum gate matrix after the value of the loss function is minimized; and in response to that the current pulse number is less than the maximum pulse number and the error is greater than the error tolerance, adding one to the current pulse number.

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