Leveraging chip variability
    1.
    发明授权

    公开(公告)号:US08412882B2

    公开(公告)日:2013-04-02

    申请号:US12819100

    申请日:2010-06-18

    IPC分类号: G06F12/00 G06F12/02

    摘要: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

    LEVERAGING CHIP VARIABILITY
    2.
    发明申请
    LEVERAGING CHIP VARIABILITY 有权
    杠杆切片变率

    公开(公告)号:US20110314210A1

    公开(公告)日:2011-12-22

    申请号:US12819100

    申请日:2010-06-18

    IPC分类号: G06F12/00 G06F12/02

    摘要: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

    摘要翻译: 描述利用芯片的可变性的实施例。 芯片的不同区域在相同工作条件下的可靠性方面不同。 可以通过在芯片的不同区域上测量误差来捕获可变性。 可以改变影响或控制芯片上的错误可能性的物理因素。 例如,提供给芯片的电压可以设置在不同的水平。 在物理因素的每个级别,对芯片进行测试,以区域内的错误。 存储区域的误差统计的一些指示,然后用于调整芯片使用的功率,调整芯片的可靠性行为,以允许应用程序控制芯片的使用方式,以计算唯一识别芯片的签名, 等等

    Random Access Memory (RAM) Based Content Addressable Memory (CAM) Management
    3.
    发明申请
    Random Access Memory (RAM) Based Content Addressable Memory (CAM) Management 失效
    基于随机存取存储器(RAM)的内容可寻址存储器(CAM)管理

    公开(公告)号:US20070186036A1

    公开(公告)日:2007-08-09

    申请号:US11734168

    申请日:2007-04-11

    申请人: Ray Bittner

    发明人: Ray Bittner

    IPC分类号: G06F12/00

    CPC分类号: G11C15/00

    摘要: A Random Access Memory (RAM) based Content Addressable Memory (CAM) architecture is disclosed. In an implementation, the CAM architecture includes a CAM data structure associated with a RAM to store one or more tags and associated data values. Each of the tags includes one or more bit fields which are utilized as an index for referencing a look-up table. One or more look-up tables may be realized for supporting memory operations facilitating efficient transfer modes available in the RAM.

    摘要翻译: 公开了一种基于随机存取存储器(RAM)的内容可寻址存储器(CAM)架构。 在实现中,CAM架构包括与RAM相关联的CAM数据结构以存储一个或多个标签和相关联的数据值。 每个标签包括一个或多个比特字段,其被用作用于引用查找表的索引。 可以实现一个或多个查找表以支持促进RAM中可用的有效传输模式的存储器操作。

    Interfacing I/O Devices with a Mobile Server
    4.
    发明申请
    Interfacing I/O Devices with a Mobile Server 审中-公开
    将I / O设备与移动服务器连接

    公开(公告)号:US20070174515A1

    公开(公告)日:2007-07-26

    申请号:US11275490

    申请日:2006-01-09

    IPC分类号: G06F13/38

    CPC分类号: H04M1/7253

    摘要: A mobile server is wirelessly communicable with at least one remote input/output (I/O) device to form a wireless personal-area network (PAN). The mobile server has at least one application program interface (API) allowing an application of arbitrary implementation on the mobile server to recognize and control at least one service implemented by the remote I/O device.

    摘要翻译: 移动服务器与至少一个远程输入/输出(I / O)设备无线通信,以形成无线个人区域网络(PAN)。 移动服务器具有允许在移动服务器上应用任意实现的至少一个应用程序接口(API)来识别和控制由远程I / O设备实现的至少一个服务。

    Direct communication between GPU and FPGA components
    5.
    发明授权
    Direct communication between GPU and FPGA components 有权
    GPU与FPGA组件之间的直接通信

    公开(公告)号:US09304730B2

    公开(公告)日:2016-04-05

    申请号:US13593129

    申请日:2012-08-23

    IPC分类号: G06F13/14 G06F3/14 G09G5/36

    摘要: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.

    摘要翻译: 系统可以包括图形处理单元(GPU)和现场可编程门阵列(FPGA)。 该系统还可以包括在FPGA外部的总线接口,并且被配置为直接在GPU和FPGA之间传送数据,而不将数据存储在中央处理单元(CPU)的存储器中作为中介操作。

    DIRECT COMMUNICATION BETWEEN GPU AND FPGA COMPONENTS
    6.
    发明申请
    DIRECT COMMUNICATION BETWEEN GPU AND FPGA COMPONENTS 有权
    GPU与FPGA组件之间的直接通信

    公开(公告)号:US20140055467A1

    公开(公告)日:2014-02-27

    申请号:US13593129

    申请日:2012-08-23

    IPC分类号: G06F13/14

    摘要: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.

    摘要翻译: 系统可以包括图形处理单元(GPU)和现场可编程门阵列(FPGA)。 该系统还可以包括在FPGA外部的总线接口,并且被配置为直接在GPU和FPGA之间传送数据,而不将数据存储在中央处理单元(CPU)的存储器中作为中介操作。

    Content addressable memory architecture
    7.
    发明申请
    Content addressable memory architecture 有权
    内容可寻址内存架构

    公开(公告)号:US20070011436A1

    公开(公告)日:2007-01-11

    申请号:US11143060

    申请日:2005-06-01

    申请人: Ray Bittner

    发明人: Ray Bittner

    IPC分类号: G06F15/00

    CPC分类号: G06F12/0895

    摘要: A content addressable memory (CAM) architecture comprises two components, a small, fast on-chip cache memory that stores data that is likely needed in the immediate future, and an off-chip main memory in normal RAM. The CAM allows data to be stored with an associated tag that is of any size and identifies the data. Via tags, waves of data are launched into a machine's computational hardware and re-associated with related tags upon return. Tags may be generated so that related data values have adjacent storage locations, facilitating fast retrieval. Typically, the CAM emits only complete operand sets. By using tags to identify unique operand sets, computations can be allowed to proceed out of order, and be recollected later for further processing. This allows greater computational speed via multiple parallel processing units that compute large sets of operand sets, or by opportunistically fetching and executing operand sets as they become available.

    摘要翻译: 内容可寻址存储器(CAM)架构包括两个组件,即存储在不久的将来可能需要的数据的小型,快速的片上高速缓存存储器和正常RAM中的片外主存储器。 CAM允许使用任何大小的关联标签存储数据并识别数据。 通过标签,数据波发射到机器的计算硬件中,并在返回时与相关标签重新关联。 可以生成标签,使得相关数据值具有相邻的存储位置,便于快速检索。 通常,CAM仅发出完整的操作数集。 通过使用标签来识别唯一的操作数集合,可以允许计算继续执行,并且稍后重新进行进一步处理。 这允许通过计算大组操作数集合的多个并行处理单元或通过在它们变得可用时机会地获取和执行操作数集合来实现更大的计算速度。

    Conditional execution via content addressable memory and parallel computing execution model
    8.
    发明申请
    Conditional execution via content addressable memory and parallel computing execution model 有权
    通过内容可寻址内存和并行计算执行模式进行条件执行

    公开(公告)号:US20060277392A1

    公开(公告)日:2006-12-07

    申请号:US11143308

    申请日:2005-06-01

    申请人: Ray Bittner

    发明人: Ray Bittner

    IPC分类号: G06F9/40

    摘要: The use of a configuration-based execution model in conjunction with a content addressable memory (CAM) architecture provides a mechanism that enables performance of a number of computing concepts, including conditional execution, (e.g., If-Then statements and while loops), function calls and recursion. If-then and while loops are implemented by using a CAM feature that emits only complete operand sets from the CAM for processing; different seed operands are generated for different conditional evaluation results, and that seed operand is matched with computed data to for an if-then branch or upon exiting a while loop. As a result, downstream operators retrieve only completed operands. Function calls and recursion are handled by using a return tag as an operand along with function parameter data into the input tag space of a function. A recursive function is split into two halves, a pre-recursive half and a post-recursive half that executes after pre-recursive calls.

    摘要翻译: 结合内容可寻址存储器(CAM)架构使用基于配置的执行模型提供了一种机制,其能够执行包括条件执行(例如,If-Then语句和while循环)的多个计算概念的功能,功能 调用和递归。 通过使用仅从CAM处理完整的操作数集合的CAM功能来实现if-then和while循环以进行处理; 为不同的条件评估结果生成不同的种子操作数,并且将种子操作数与计算数据匹配,以供if-then分支或退出while循环。 因此,下游运营商仅检索完成的操作数。 通过使用返回标记作为操作数以及函数参数数据到函数的输入标签空间来处理函数调用和递归。 递归函数分为两部分,一个预递归半部分和一个在递归递归调用之后执行的递归递归后半部分。

    Execution model for parallel computing
    10.
    发明申请
    Execution model for parallel computing 有权
    并行计算的执行模型

    公开(公告)号:US20060277391A1

    公开(公告)日:2006-12-07

    申请号:US11143307

    申请日:2005-06-01

    申请人: Ray Bittner

    发明人: Ray Bittner

    IPC分类号: G06F9/40

    CPC分类号: G06F9/4494

    摘要: A dataflow graph is split into sub-graphs referred to as configurations, each configuration comprising computational hardware containing elements that operate on operand sets. A configuration executes by consuming completed operand sets from a designated input tag space (e.g., in a content addressable memory) until the operand sets are exhausted. At that point, the configuration is replaced by another configuration. The execution of a configuration may be triggered by system events, including by the completion of one or more other configurations. Each configuration has a list of inputs on which it depends to form complete operand sets. As other configurations that provide an input complete, a dependency flag is set in each dependent configuration. As each flag is set, the complete set of flags is checked for that configuration; if all the input flags for any configuration are set, then that configuration is scheduled for execution.

    摘要翻译: 数据流图被分为称为配置的子图,每个配置包括包含操作数集合的元素的计算硬件。 通过从指定的输入标签空间(例如,在内容可寻址存储器)中消耗完成的操作数集,直到操作数集合被耗尽来执行配置。 在这一点上,配置被另一个配置所取代。 配置的执行可以由系统事件触发,包括完成一个或多个其他配置。 每个配置都有一个输入列表,它依赖于其形成完整的操作数集。 作为提供输入完成的其他配置,在每个相关配置中设置依赖标志。 当每个标志被设置时,对该配置检查完整的标志集合; 如果任何配置的所有输入标志都被设置,那么该配置被安排执行。