公开(公告)号：US09934045B1

公开(公告)日：2018-04-03

申请号：US14684399

申请日：2015-04-12

Applicant: BiTMICRO Networks, Inc.

Inventor： Alvin Anonuevo Manlapat ,  Ian Victor Pasion Beleno

IPC: G06F1/12 ,  G06F9/44 ,  G06F1/24 ,  G06F12/02 ,  G11C7/10

CPC classification number: G06F9/4401 ,  G06F1/24 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C7/1072 ,  G11C8/16

Abstract: In an embodiment of the invention, an apparatus comprises an embedded system comprising: a processor configured to execute firmware; a random access memory (RAM) configured to store firmware and a multi-port memory controller configured to interface with the RAM; a power-on reset (POR) sequencer configured to control a boot process of the embedded system; a nonvolatile memory configured to store data used by the POR sequencer in the boot process and a nonvolatile memory controller configured to interface with the nonvolatile memory; a direct memory access (DMA) controller configured initiate and track data transfers; and a configuration and status register (CSR) controller configured to access modules in the embedded system.

公开(公告)号：US09858084B2

公开(公告)日：2018-01-02

申请号：US14217399

申请日：2014-03-17

Applicant: BITMICRO Networks, Inc.

Inventor： Alvin Anonuevo Manlapat ,  Ian Victor Pasion Beleno

IPC: G06F1/12 ,  G06F9/44 ,  G06F1/24

CPC classification number: G06F9/4401 ,  G06F1/12 ,  G06F1/24

Abstract: A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers.Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness. Through the use of the Power-On Reset Sequencer module, integrity of program code and user data used in the boot up process can be verified thus providing a resilient boot up sequence.

公开(公告)号：US10120694B2

公开(公告)日：2018-11-06

申请号：US14217365

申请日：2014-03-17

Applicant: BiTMICRO Networks, Inc.

Inventor： Alvin Anonuevo Manlapat ,  Ian Victor Pasion Beleno

IPC: G06F1/24 ,  G06F9/44 ,  G06F9/4401 ,  G06F1/12

Abstract: A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers.Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness. Through the use of the Power-On Reset Sequencer module, integrity of program code and user data used in the boot up process can be verified thus providing a resilient boot up sequence.The present invention provides a mechanism for booting up a system using a minimum amount of nonvolatile memory. This method also enables the embedded system to initialize all configuration registers even before any of the CPUs of the system is brought out of reset. The embedded system consists of multiple controller chips or a single controller chip. The embedded system can have a single or multiple central processing units.