公开(公告)号：US06462591B2

公开(公告)日：2002-10-08

申请号：US09882420

申请日：2001-06-14

申请人： Billy Wayne Garrett, Jr. ,  John B. Dillon ,  by Nancy David Dillon ,  Michael Tak-Kei Ching ,  William F. Stonecypher ,  Andy Peng-Pui Chan ,  Matthew M. Griffin

发明人： Billy Wayne Garrett, Jr. ,  John B. Dillon ,  by Nancy David Dillon ,  Michael Tak-Kei Ching ,  William F. Stonecypher ,  Andy Peng-Pui Chan ,  Matthew M. Griffin

IPC分类号： H03B100

CPC分类号： G11C7/1057 ,  G06F13/4077 ,  G11C7/1051 ,  G11C7/106 ,  H03K19/00384 ,  H03K19/018585 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/0298

摘要： A semiconductor memory device including an array of memory cells. The memory device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. The memory device further includes a voltage divider coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. The memory device further includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.

摘要翻译： 一种包括存储单元阵列的半导体存储器件。 存储器件包括耦合到第一输出端的第一输出驱动器和耦合到第二输出端的第二输出驱动器。 存储器件还包括耦合在第一和第二输出端子之间的分压器，以基于存在于第一输出端子上的电压电平和第二输出端子上存在的电压电平产生控制电压。 存储器件还包括耦合到分压器的比较器，用于将控制电压与参考电压进行比较，其中基于控制电压和参考电压之间的比较来调节第一输出驱动器的电压摆幅量。

公开(公告)号：US06356975B1

公开(公告)日：2002-03-12

申请号：US09169526

申请日：1998-10-09

申请人： Richard M. Barth ,  Ely K. Tsern ,  Mark A. Horowitz ,  Donald C. Stark ,  Craig E. Hampel ,  Frederick A. Ware ,  John B. Dillon ,  by Nancy David Dillon

发明人： Richard M. Barth ,  Ely K. Tsern ,  Mark A. Horowitz ,  Donald C. Stark ,  Craig E. Hampel ,  Frederick A. Ware ,  John B. Dillon ,  by Nancy David Dillon

IPC分类号： G06F1200

CPC分类号： G11C7/1006 ,  G06F13/1615 ,  G11C7/10 ,  G11C7/1039 ,  G11C8/12 ,  G11C11/4076

摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.