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14 条记录 (耗时 0.018 秒)

    Transparent multi-mode PAM interface
    1.
    发明授权
    Transparent multi-mode PAM interface 有权
    透明多模PAM接口

    公开(公告)号：US07308058B2

    公开(公告)日：2007-12-11

    申请号：US10805413

    申请日：2004-03-19

    申请人： Jared L. Zerbe ,  Carl W. Werner ,  William F. Stonecypher ,  Fred F. Chen

    发明人： Jared L. Zerbe ,  Carl W. Werner ,  William F. Stonecypher ,  Fred F. Chen

    IPC分类号： H03K9/02

    CPC分类号： H04L27/08 ,  H04L1/0003 ,  H04L5/1438 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/4917 ,  H04L2025/03585

    摘要： Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols is constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.

    摘要翻译： 提供了一种用于高速，多模式PAM符号传输的方法和装置。 多模式PAM输出驱动器根据PAM模式信号的状态驱动一个或多个符号，用于一个或多个符号的PAM调制中使用的级别数。 另外，一个或多个符号以符号率被驱动，符号率是根据PAM模式信号选择的，使得驱动符号的数据速率相对于PAM模式信号的状态的变化是恒定的。 还提供了用于在给定物理环境中确定用于符号传输和接收的PAM最优数量的方法。

    Memory system including a memory device having a controlled output driver characteristic
    4.
    发明授权
    Memory system including a memory device having a controlled output driver characteristic 失效
    存储器系统，包括具有受控输出驱动器特性的存储器件

    公开(公告)号：US06608507B2

    公开(公告)日：2003-08-19

    申请号：US10230931

    申请日：2002-08-29

    申请人： Billy Wayne Garrett, Jr. ,  John B. Dillon ,  Michael Tak-Kei Ching ,  William F. Stonecypher ,  Andy Peng-Pui Chan ,  Matthew M. Griffin

    发明人： Billy Wayne Garrett, Jr. ,  John B. Dillon ,  Michael Tak-Kei Ching ,  William F. Stonecypher ,  Andy Peng-Pui Chan ,  Matthew M. Griffin

    IPC分类号： H03B100

    CPC分类号： G11C7/1057 ,  G06F13/4077 ,  G11C7/1051 ,  G11C7/106 ,  H03K19/00384 ,  H03K19/018585 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/0298

    摘要： A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode. The memory device is operable in a normal read operation upon exiting the calibration mode. During the normal read operation, the first output driver is operable to output data onto the first signal line in accordance with the calibrated voltage swing level.

    摘要翻译： 一种存储系统和调整包含在存储器系统中的存储器件的输出驱动器特性的方法。 该方法包括向存储器件提供指定校准模式的命令，并且在校准模式期间，使用第一输出驱动器将电压电平驱动到第一信号线上。 第一电压电平是从驱动第一信号线上的电压电平的第一输出驱动器产生的电压摆幅的量导出的。 该方法还包括：主动地将第一比较器耦合到第一信号线; 当所述第一比较器耦合到所述第一信号线时，使用所述第一比较器将所述第一电压电平与参考电压进行比较; 并且调整电压摆幅的量以达到校准的电压摆幅水平。 此外，该方法包括在退出校准模式时将第一比较器与第一信号线主动隔离。 存储器件在退出校准模式时可在正常读取操作中操作。 在正常读取操作期间，第一输出驱动器可操作以根据校准的电压摆幅电平将数据输出到第一信号线上。

    Method and apparatus for fail-safe resynchronization with minimum latency
    9.
    发明授权
    Method and apparatus for fail-safe resynchronization with minimum latency 失效
    具有最小延迟的故障安全重新同步的方法和装置

    公开(公告)号：US06473439B1

    公开(公告)日：2002-10-29

    申请号：US09169372

    申请日：1998-10-09

    申请人： Jared LeVan Zerbe ,  Michael Tak-kei Ching ,  Abhijit M. Abhyankar ,  Richard M. Barth ,  Andy Peng-Pui Chan ,  Paul G. Davis ,  William F. Stonecypher

    发明人： Jared LeVan Zerbe ,  Michael Tak-kei Ching ,  Abhijit M. Abhyankar ,  Richard M. Barth ,  Andy Peng-Pui Chan ,  Paul G. Davis ,  William F. Stonecypher

    IPC分类号： H04J306

    CPC分类号： G06F1/12 ,  G06F13/423 ,  H03L7/085 ,  H04L7/0012 ,  H04L7/0045 ,  H04L7/0054 ,  H04L7/02 ,  H04L7/0337

    摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

    摘要翻译： 公开了一种在两个同步（相同频率，不同相位）时钟域之间实现最小延迟数据传输的方法和电路。 该电路支持两个时钟域之间的任意相位关系，并且在保持相同的输出数据延迟之后容忍初始化之后的温度和电压偏移。 在一个实施例中，该电路用于总线系统以将数据从接收域，时钟重新传输到发射域时钟。 在这种系统中，这两个时钟之间的相位关系由设备总线位置设置，因此不是精确的。 通过支持任意相位重新同步，本公开允许理论上无限长的总线长度，从而不限制器件数量，以及沿着总线的器件的任意放置。 这最终允许为很长的总线支持多个延迟域。