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公开(公告)号：US06922092B2
公开(公告)日：2005-07-26
申请号：US10731718
申请日：2003-12-08
IPC分类号： G11C7/10 , H03B1/00 , H03K17/16 , H03K19/003 , H03K5/12
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
摘要翻译： 输出驱动器具有输出多路复用器和输出电流驱动器。 输出多路复用器接收数据信号并输出q-节点信号。 输出电流驱动器接收q-节点信号并根据q-节点信号驱动总线。 输出多路复用器以各种方式处理数据信号以产生q-结点信号。 输出电流驱动器响应于当前控制位以选择输出驱动电流的量。 此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。
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公开(公告)号：US07352234B2
公开(公告)日：2008-04-01
申请号：US11625711
申请日：2007-01-22
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon, legal representative , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： John B. Dillon
IPC分类号： G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
摘要翻译： 使用输出驱动电路和电流控制技术，以便于低噪声的高速总线与高速动态RAM（DRAM）接口。 该架构包括以下组件：输入隔离块（120），模拟分压器（104），输入比较器（125），采样锁存器（130），电流控制计数器（115）和按位输出驱动器 （输出驱动器A107和输出驱动器B111）。
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3.发明授权公开(公告)号：US07288973B2
公开(公告)日：2007-10-30
申请号：US11237276
申请日：2005-09-27
申请人： Jared LeVan Zerbe , Michael Tak-kei Ching , Abhijit M. Abhyankar , Richard M. Barth , Andy Peng-Pui Chan , Paul G. Davis , William F. Stonecypher
发明人： Jared LeVan Zerbe , Michael Tak-kei Ching , Abhijit M. Abhyankar , Richard M. Barth , Andy Peng-Pui Chan , Paul G. Davis , William F. Stonecypher
IPC分类号： H03L7/00
CPC分类号： G06F1/12 , G06F13/423 , H03L7/085 , H04L7/0012 , H04L7/0045 , H04L7/0054 , H04L7/02 , H04L7/0337
摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.
摘要翻译： 公开了一种在两个同步（相同频率，不同相位）时钟域之间实现最小延迟数据传输的方法和电路。 该电路支持两个时钟域之间的任意相位关系，并且在保持相同的输出数据延迟之后容忍初始化之后的温度和电压偏移。 在一个实施例中，该电路用于总线系统以将数据从接收域，时钟重新传输到发射域时钟。 在这种系统中，这两个时钟之间的相位关系由设备总线位置设置，因此不是精确的。 通过支持任意相位重新同步，本公开允许理论上无限长的总线长度，从而不限制器件数量，以及沿着总线的器件的任意放置。 这最终允许为很长的总线支持多个延迟域。
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公开(公告)号：US07091761B2
公开(公告)日：2006-08-15
申请号：US11148783
申请日：2005-06-08
IPC分类号： H03K5/12
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
摘要翻译： 输出驱动器具有输出多路复用器和输出电流驱动器。 输出多路复用器接收数据信号并输出q-节点信号。 输出电流5河接收q节点信号，并根据q-节点信号驱动总线。 输出多路复用器以各种方式处理数据信号以产生q-结点信号。 输出电流驱动器响应于当前控制位以选择输出驱动电流的量。 此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。
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公开(公告)号：US06661268B2
公开(公告)日：2003-12-09
申请号：US10014650
申请日：2001-12-11
IPC分类号： H03K512
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
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公开(公告)号：US06294934B1
公开(公告)日：2001-09-25
申请号：US09559115
申请日：2000-04-26
申请人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： H03B100
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/028 , H04L25/0282 , H04L25/0298
摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
摘要翻译： 使用输出驱动电路和电流控制技术，以便于低噪声的高速总线与高速动态RAM（DRAM）接口。 该架构包括以下组件：输入隔离块（120），模拟分压器（104），输入比较器（125），采样锁存器（130），电流控制计数器（115）和按位输出驱动器 （输出驱动器A107和输出驱动器B111）。
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公开(公告)号：US6094075A
公开(公告)日：2000-07-25
申请号：US141675
申请日：1998-08-27
申请人： Billy Wayne Garrett, Jr. , John B. Dillon, deceased , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon, deceased , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： G06F13/40 , G11C7/10 , H03K19/003 , H03K19/0185 , H04L25/02 , H03B1/00
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/028 , H04L25/0282 , H04L25/0266 , H04L25/0272 , H04L25/0298
摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
摘要翻译： 使用输出驱动电路和电流控制技术，以便于低噪声的高速总线与高速动态RAM（DRAM）接口。 该架构包括以下组件：输入隔离块（120），模拟分压器（104），输入比较器（125），采样锁存器（130），电流控制计数器（115）和按位输出驱动器 （输出驱动器A107和输出驱动器B111）。
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公开(公告)号：US07167039B2
公开(公告)日：2007-01-23
申请号：US10890972
申请日：2004-07-14
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon, legal representative , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.
摘要翻译： 一种操作包括输出驱动器的集成电路的方法。 该方法包括将值存储在寄存器中，其中该值表示输出驱动器的电压摆幅设置。 输出驱动器的电压摆幅设置使用保持表示电压摆幅设置的更新的计数值的计数器进行调整。 根据指示对电压摆幅设定的调整的信号来更新计数值。 此外，提供了包括输出驱动器，寄存器和计数器的集成电路存储器件。 计数器响应于指示调整计数值的方向的信号来更新计数值。
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9.发明授权公开(公告)号：US06473439B1
公开(公告)日：2002-10-29
申请号：US09169372
申请日：1998-10-09
申请人： Jared LeVan Zerbe , Michael Tak-kei Ching , Abhijit M. Abhyankar , Richard M. Barth , Andy Peng-Pui Chan , Paul G. Davis , William F. Stonecypher
发明人： Jared LeVan Zerbe , Michael Tak-kei Ching , Abhijit M. Abhyankar , Richard M. Barth , Andy Peng-Pui Chan , Paul G. Davis , William F. Stonecypher
IPC分类号： H04J306
CPC分类号： G06F1/12 , G06F13/423 , H03L7/085 , H04L7/0012 , H04L7/0045 , H04L7/0054 , H04L7/02 , H04L7/0337
摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.
摘要翻译： 公开了一种在两个同步（相同频率，不同相位）时钟域之间实现最小延迟数据传输的方法和电路。 该电路支持两个时钟域之间的任意相位关系，并且在保持相同的输出数据延迟之后容忍初始化之后的温度和电压偏移。 在一个实施例中，该电路用于总线系统以将数据从接收域，时钟重新传输到发射域时钟。 在这种系统中，这两个时钟之间的相位关系由设备总线位置设置，因此不是精确的。 通过支持任意相位重新同步，本公开允许理论上无限长的总线长度，从而不限制器件数量，以及沿着总线的器件的任意放置。 这最终允许为很长的总线支持多个延迟域。
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10.发明授权公开(公告)号：US06462591B2
公开(公告)日：2002-10-08
申请号：US09882420
申请日：2001-06-14
申请人： Billy Wayne Garrett, Jr. , John B. Dillon , by Nancy David Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon , by Nancy David Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： H03B100
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/028 , H04L25/0282 , H04L25/0298
摘要： A semiconductor memory device including an array of memory cells. The memory device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. The memory device further includes a voltage divider coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. The memory device further includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.
摘要翻译： 一种包括存储单元阵列的半导体存储器件。 存储器件包括耦合到第一输出端的第一输出驱动器和耦合到第二输出端的第二输出驱动器。 存储器件还包括耦合在第一和第二输出端子之间的分压器，以基于存在于第一输出端子上的电压电平和第二输出端子上存在的电压电平产生控制电压。 存储器件还包括耦合到分压器的比较器，用于将控制电压与参考电压进行比较，其中基于控制电压和参考电压之间的比较来调节第一输出驱动器的电压摆幅量。
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