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公开(公告)号：US07673074B1
公开(公告)日：2010-03-02
申请号：US10421495
申请日：2003-04-22
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177
CPC分类号： H04L69/16 , H04L69/12 , H04L69/161
摘要： The avoidance of port collisions in a hardware-accelerated network protocol, such as Transmission Control Protocol (TCP)/Internet Protocol (IP), is disclosed. In one example, a hardware-accelerated host bus adaptor (HBA) offloads protocol processing from a host computer's operating system. However, a port collision occurs if a non-accelerated host TCP/IP stack and a hardware accelerated host bus adapter TCP/IP stack choose the same port for establishing a network connection. In a double-ended TCP/IP acceleration connection, a unique TCP port is bound to the accelerated TCP/IP stack. In a single-ended TCP/IP acceleration connection, either the host TCP/IP stack is prevented from using that port or a non-accelerated connection is associated with an accelerated connection without binding a port.
摘要翻译： 披露了在硬件加速网络协议（如传输控制协议（TCP）/网际协议（IP））中避免端口冲突。 在一个示例中，硬件加速主机总线适配器（HBA）从主机的操作系统卸载协议处理。 但是，如果非加速主机TCP / IP堆栈和硬件加速主机总线适配器TCP / IP堆栈选择相同的端口建立网络连接，则会发生端口冲突。 在双端TCP / IP加速连接中，唯一的TCP端口绑定到加速TCP / IP堆栈。 在单端TCP / IP加速连接中，禁止主机TCP / IP堆栈使用该端口，或者非加速连接与加速连接相关联，而不绑定端口。
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公开(公告)号：US07283471B2
公开(公告)日：2007-10-16
申请号：US10386642
申请日：2003-03-11
申请人： Maria C. Gutierrez , Shawn Adam Clayton , David R. Follett , Harold E. Roman , Nitin D. Godiwala , Richard F. Prohaska , James B. Williams
发明人： Maria C. Gutierrez , Shawn Adam Clayton , David R. Follett , Harold E. Roman , Nitin D. Godiwala , Richard F. Prohaska , James B. Williams
IPC分类号： H04L1/00
CPC分类号： H04L12/5602 , H04L47/10 , H04L47/16 , H04L47/263 , H04L47/30 , H04L2012/5635 , H04L2012/5651 , H04L2012/5682 , H04Q11/0478
摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.
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公开(公告)号：US06570850B1
公开(公告)日：2003-05-27
申请号：US09065118
申请日：1998-04-23
申请人： Maria C. Gutierrez , Shawn A. Clayton , David R. Follett , Nitin D. Godiwala , Richard F. Prohaska , Harold E. Roman , James B. Williams
发明人： Maria C. Gutierrez , Shawn A. Clayton , David R. Follett , Nitin D. Godiwala , Richard F. Prohaska , Harold E. Roman , James B. Williams
IPC分类号： H04Q1104
CPC分类号： H04L12/5602 , H04L47/10 , H04L47/16 , H04L47/263 , H04L47/30 , H04L2012/5635 , H04L2012/5651 , H04L2012/5682 , H04Q11/0478
摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.
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公开(公告)号：US07953876B1
公开(公告)日：2011-05-31
申请号：US10651426
申请日：2003-08-28
申请人： Harold E. Roman , James B. Williams
发明人： Harold E. Roman , James B. Williams
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L69/163
摘要： A method and system comprising a host system and a host bus adapter (HBA). The HBA is configured to handle a Virtual Interface and Transmission Control Protocol (TCP)/Internet Protocol (IP) processing for applications running on the host system.
摘要翻译： 一种包括主机系统和主机总线适配器（HBA）的方法和系统。 HBA被配置为处理在主机系统上运行的应用的虚拟接口和传输控制协议（TCP）/因特网协议（IP）处理。
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公开(公告)号：US5313476A
公开(公告)日：1994-05-17
申请号：US723284
申请日：1991-06-28
IPC分类号： G06F1/10 , G06F11/267 , G11B11/00
CPC分类号： G06F11/267 , G06F1/10
摘要： A clock security ring provides improved clock system error detection and (a.c.) fault isolation. The clock security ring is formed by a plurality of fault detection circuits and a plurality of error collection circuits each receiving inputs from respective subsets of the plurality of fault detection circuits. The error collection circuits comprise a logical network which provides a detected fault output for any fault pattern which leaves at least one fault detection circuit in a predefined correct state. Each of the subsets of fault detection circuits has an arbitrary grouping of fault detection circuits plus one fault detection circuit from an adjacent subset to thereby form a ring structure. The outputs of the error collection circuits are analyzed to provide fault isolation.
摘要翻译： 时钟安全环提供改进的时钟系统错误检测和（a.c.）故障隔离。 时钟安全环由多个故障检测电路和多个错误收集电路组成，每个错误收集电路接收来自多个故障检测电路的各个子集的输入。 错误收集电路包括逻辑网络，其为任何故障模式提供检测到的故障输出，所述故障模式使至少一个故障检测电路处于预定义的正确状态。 故障检测电路的每个子集具有故障检测电路的任意分组加上来自相邻子集的一个故障检测电路，从而形成环结构。 分析错误收集电路的输出以提供故障隔离。
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