-
公开(公告)号：US20130111141A1
公开(公告)日：2013-05-02
申请号：US13285629
申请日：2011-10-31
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/08
摘要： A network processor includes multiple processor cores for processing packet data. In order to provide the processor cores with access to a memory subsystem, an interconnect circuit directs communications between the processor cores and the L2 Cache and other memory devices. The processor cores are divided into several groups, each group sharing an individual bus, and the L2 Cache is divided into a number of banks, each bank having access to a separate bus. The interconnect circuit processes requests to store and retrieve data from the processor cores across multiple buses, and processes responses to return data from the cache banks. As a result, the network processor provides high-bandwidth memory access for multiple processor cores.
摘要翻译： 网络处理器包括用于处理分组数据的多个处理器核。 为了向处理器核提供对存储器子系统的访问，互连电路指导处理器核与L2 Cache和其他存储器件之间的通信。 处理器核心分为几组，每组共享一条单独的总线，二级缓存分为多个银行，每个银行都可以访问单独的总线。 互连电路处理在多个总线上存储和检索来自处理器核心的数据的请求，并处理从缓存存储器返回数据的响应。 因此，网络处理器为多个处理器内核提供高带宽存储器访问。
-
公开(公告)号：US09612934B2
公开(公告)日：2017-04-04
申请号：US13284289
申请日：2011-10-28
CPC分类号： G06F11/3495 , G06F1/3203 , G06F3/16 , G06F11/349 , G06F12/084 , G06F13/385 , G06F13/4022
摘要： A network processor includes a cache and a several groups of processors for accessing the cache. A memory interconnect provides for connecting the processors to the cache via a plurality of memory buses. A number of trace buffers are also connected to the bus and operate to store information regarding commands and data transmitted across the bus. The trace buffers share a common address space, thereby enabling access to the trace buffers as a single entity.
-
公开(公告)号：US09330002B2
公开(公告)日：2016-05-03
申请号：US13285629
申请日：2011-10-31
CPC分类号： G06F12/0813 , G06F12/08
摘要： A network processor includes multiple processor cores for processing packet data. In order to provide the processor cores with access to a memory subsystem, an interconnect circuit directs communications between the processor cores and the L2 Cache and other memory devices. The processor cores are divided into several groups, each group sharing an individual bus, and the L2 Cache is divided into a number of banks, each bank having access to a separate bus. The interconnect circuit processes requests to store and retrieve data from the processor cores across multiple buses, and processes responses to return data from the cache banks. As a result, the network processor provides high-bandwidth memory access for multiple processor cores.
摘要翻译： 网络处理器包括用于处理分组数据的多个处理器核。 为了向处理器核提供对存储器子系统的访问，互连电路指导处理器核与L2 Cache和其他存储器件之间的通信。 处理器核心分为几组，每组共享一条单独的总线，二级缓存分为多个银行，每个银行都可以访问单独的总线。 互连电路处理在多个总线上存储和检索来自处理器核心的数据的请求，并处理从缓存存储器返回数据的响应。 因此，网络处理器为多个处理器内核提供高带宽存储器访问。
-
公开(公告)号：US20130111073A1
公开(公告)日：2013-05-02
申请号：US13284289
申请日：2011-10-28
CPC分类号： G06F11/3495 , G06F1/3203 , G06F3/16 , G06F11/349 , G06F12/084 , G06F13/385 , G06F13/4022
摘要： A network processor includes a cache and a several groups of processors for accessing the cache. A memory interconnect provides for connecting the processors to the cache via a plurality of memory buses. A number of trace buffers are also connected to the bus and operate to store information regarding commands and data transmitted across the bus. The trace buffers share a common address space, thereby enabling access to the trace buffers as a single entity.
摘要翻译： 网络处理器包括高速缓存和用于访问高速缓存的几组处理器。 存储器互连提供了通过多个存储器总线将处理器连接到高速缓存。 多个跟踪缓冲器也连接到总线，并用于存储有关通过总线传输的命令和数据的信息。 跟踪缓冲区共享公共地址空间，从而使跟踪缓冲区能够作为单个实体访问。
-
-
-
搜索结果
4 条记录 (耗时 0.02 秒)
