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公开(公告)号:US20140226258A1
公开(公告)日:2014-08-14
申请号:US14180842
申请日:2014-02-14
Applicant: Brandon Summey , Peter Blais , Yanming Liu
Inventor: Brandon Summey , Peter Blais , Yanming Liu
CPC classification number: H01G4/38 , H01G4/005 , H01G4/008 , H01G9/0029 , H01G9/055 , Y10T29/302 , Y10T29/43
Abstract: An improved array of capacitors is provided wherein the improvement includes improved electrical properties and improved packing density. The array has an anode foil and a dielectric on a surface of the anode foil. A multiplicity of areas are defined on the dielectric wherein each area is circumvented by an isolation material and the isolation material extends through the dielectric. A conductive cathode layer in each area forms a capacitive couple. At least one substrate vacancy is in the anode foil and the substrate vacancy electrically isolates adjacent anodes of adjacent capacitive couples. A carrier film is attached to the capacitive couples.
Abstract translation: 提供了一种改进的电容器阵列,其中改进包括改进的电性能和改进的包装密度。 该阵列在阳极箔的表面上具有阳极箔和电介质。 在电介质上限定多个区域,其中每个区域被隔离材料绕过,隔离材料延伸通过电介质。 每个区域中的导电阴极层形成电容耦合。 阳极箔中至少有一个衬底空位,并且衬底空位电隔离相邻电容耦合的相邻阳极。 载体膜连接到电容对。
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公开(公告)号:US20090310280A1
公开(公告)日:2009-12-17
申请号:US12138898
申请日:2008-06-13
Applicant: John D. Prymak , Peter Blais , George Haddox , Michael Prevallet , Jim Piller , Chris Stolarski , Chris Wayne
Inventor: John D. Prymak , Peter Blais , George Haddox , Michael Prevallet , Jim Piller , Chris Stolarski , Chris Wayne
IPC: H01G4/38
Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.
Abstract translation: 一种电容器组件,其具有带有第一面和第二面的基板。 多个电容器安装在第一面上,其中每个电容器具有与第一引线相反极性的第一引线和第二引线。 桥与多个第一引线电接触。 树与桥接电接触,其中树通过基底的通孔并与第二面的第一迹线电接触。 第二迹线在第二面上,其中第二引线与第二迹线电接触。
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公开(公告)号:US08125766B2
公开(公告)日:2012-02-28
申请号:US12138898
申请日:2008-06-13
Applicant: John D. Prymak , Peter Blais , George Haddox , Michael Prevallet , Jim Piller , Chris Stolarski , Chris Wayne
Inventor: John D. Prymak , Peter Blais , George Haddox , Michael Prevallet , Jim Piller , Chris Stolarski , Chris Wayne
IPC: H01G4/38
Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.
Abstract translation: 一种电容器组件,其具有带有第一面和第二面的基板。 多个电容器安装在第一面上,其中每个电容器具有与第一引线相反极性的第一引线和第二引线。 桥与多个第一引线电接触。 树与桥接电接触,其中树通过基底的通孔并与第二面的第一迹线电接触。 第二迹线在第二面上,其中第二引线与第二迹线电接触。
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公开(公告)号:US20080123251A1
公开(公告)日:2008-05-29
申请号:US11605160
申请日:2006-11-28
Applicant: Michael S. Randall , Peter Blais , Pascal Pinceloup , Daniel J. Skamser , Abhijit Gurav , Azizuddin Tajuddin , John T. Kinard , Philip Lessner
Inventor: Michael S. Randall , Peter Blais , Pascal Pinceloup , Daniel J. Skamser , Abhijit Gurav , Azizuddin Tajuddin , John T. Kinard , Philip Lessner
IPC: H01G9/00
CPC classification number: H01G9/15 , H01G9/0029 , H01G9/0032 , H01G9/04
Abstract: A process for forming a capacitive couple. The process includes forming a highly porous body of a conducting material with interior struts and voids in electrical contact. A dielectric layer is formed in the voids on the struts with a material having a dielectric constant above 100. An insulating layer is formed on the struts not covered by the dielectric layer. A conductive layer is formed on the dielectric layer and on the insulating layer.
Abstract translation: 一种用于形成电容耦合的过程。 该方法包括形成具有内部支柱和电气接触的空隙的导电材料的高度多孔体。 在介质常数高于100的材料上,在支柱上的空隙中形成电介质层。绝缘层形成在未被电介质层覆盖的支柱上。 导电层形成在绝缘层和绝缘层上。
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公开(公告)号:US07280342B1
公开(公告)日:2007-10-09
申请号:US11639796
申请日:2006-12-15
Applicant: Michael S. Randall , Allen Hill , Peter Blais , Garry Renner , Randal Vaughan , Azizuddin Tajuddin
Inventor: Michael S. Randall , Allen Hill , Peter Blais , Garry Renner , Randal Vaughan , Azizuddin Tajuddin
Abstract: A low inductance multi-layer capacitor. The capacitor comprises interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate comprises two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.
Abstract translation: 低电感多层电容器。 电容器包括交错并联的内部电极板,其间具有电介质。 每个内部电极板包括两个引出片,并且通常为T形。 第一外部电极端子电连接到偶数内部电极板的引出接线片,第二外部电极端子电连接到奇数内部电极板的引出接线片。 外部电极端子位于电容器的公共第一外表面和公共相对的第二外表面上。
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公开(公告)号:US20070165361A1
公开(公告)日:2007-07-19
申请号:US11639796
申请日:2006-12-15
Applicant: Michael S. Randall , Allen Hill , Peter Blais , Garry Renner , Randal Vaughan , Azizuddin Tajuddin
Inventor: Michael S. Randall , Allen Hill , Peter Blais , Garry Renner , Randal Vaughan , Azizuddin Tajuddin
IPC: H01G4/228
Abstract: A low inductance multi-layer capacitor. The capacitor comprises interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate comprises two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.
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