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公开(公告)号：US20080224733A1
公开(公告)日：2008-09-18
申请号：US11684890
申请日：2007-03-12
CPC分类号： H03K19/09429
摘要： The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode.
摘要翻译： 这里的发明涉及用于与I / O电路一起使用的本发明的总线保持器和逻辑电路，例如用于I / O缓冲器电路的接收器侧。 本发明的电路将IC功能的一条数据线连接到三态总线的一条线路（每总线或线路的一位数据）。 母线保护器和逻辑控制电路与I / O功能驱动器保持隔离，并且响应于通常由IC或SOC提供的三态信号（TS）或正常I / O接收器中的I / O电路 侧面操作。 本发明的总线保持器和逻辑电路在存在三态使能信号的情况下，有选择地使驱动器输出焊盘处于三状态，上拉状态，下拉状态和总线保持模式状态，并且是 当I / O总线驱动缓冲电路处于驱动模式时禁用。
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公开(公告)号：US07474124B2
公开(公告)日：2009-01-06
申请号：US11684890
申请日：2007-03-12
IPC分类号： H03K17/16
CPC分类号： H03K19/09429
摘要： The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode.
摘要翻译： 这里的发明涉及用于与I / O电路一起使用的本发明的总线保持器和逻辑电路，例如用于I / O缓冲器电路的接收器侧。 本发明的电路将IC功能的一条数据线连接到三态总线的一条线路（每总线或线路的一位数据）。 母线保护器和逻辑控制电路与I / O功能驱动器保持隔离，并且响应于通常由IC或SOC提供的三态信号（TS）或正常I / O接收器中的I / O电路 侧面操作。 本发明的总线保持器和逻辑电路在存在三态使能信号的情况下，有选择地使驱动器输出焊盘处于三状态，上拉状态，下拉状态和总线保持模式状态，并且是 当I / O总线驱动缓冲电路处于驱动模式时禁用。
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