公开(公告)号：US20100287339A1

公开(公告)日：2010-11-11

申请号：US12437624

申请日：2009-05-08

申请人： Bret Ronald Olszewski ,  Steven Wayne White

发明人： Bret Ronald Olszewski ,  Steven Wayne White

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842

摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

摘要翻译： 通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联 的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及在所述新的高速缓存行条目处高速缓存所述数据，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

公开(公告)号：US08195879B2

公开(公告)日：2012-06-05

申请号：US12437624

申请日：2009-05-08

申请人： Bret Ronald Olszewski ,  Steven Wayne White

发明人： Bret Ronald Olszewski ,  Steven Wayne White

IPC分类号： G06F12/08

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842

摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

摘要翻译： 通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联 的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及在所述新的高速缓存行条目处高速缓存所述数据，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

公开(公告)号：US20120151146A1

公开(公告)日：2012-06-14

申请号：US13398292

申请日：2012-02-16

申请人： Bret Ronald Olszewski ,  Steven Wayne White

发明人： Bret Ronald Olszewski ,  Steven Wayne White

IPC分类号： G06F12/08

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842

摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

摘要翻译： 通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联 的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及在所述新的高速缓存行条目处高速缓存所述数据，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

公开(公告)号：US08458401B2

公开(公告)日：2013-06-04

申请号：US13398443

申请日：2012-02-16

申请人： Bret Ronald Olszewski ,  Steven Wayne White

发明人： Bret Ronald Olszewski ,  Steven Wayne White

IPC分类号： G06F12/08

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842

摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein the shared cache memory is effectively shared on a line-by-line basis among the plurality of logical processing partitions of the multi-core processor.

摘要翻译： 通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联 的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及将所述数据缓存在所述新的高速缓存行条目上，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

公开(公告)号：US08447929B2

公开(公告)日：2013-05-21

申请号：US13398292

申请日：2012-02-16

申请人： Bret Ronald Olszewski ,  Steven Wayne White

发明人： Bret Ronald Olszewski ,  Steven Wayne White

IPC分类号： G06F15/16

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842

摘要： Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.

摘要翻译： 通过将多个唯一的逻辑处理分区标识符接收到多核处理器的注册来管理和控制多核处理器高速缓冲存储器与逻辑分区的关联性，每个标识符与一个或多个核上的逻辑处理分区相关联 的多核处理器; 响应于共享的高速缓存存储器未命中，识别高速缓存目录中与所述地址相关联的数据的位置，所述共享高速缓存存储器是多路组合的; 将新的高速缓存行条目与数据和所注册的唯一逻辑处理分区标识符之一相关联; 修改缓存目录以反映关联; 以及在所述新的高速缓存行条目处高速缓存所述数据，其中所述共享高速缓冲存储器在所述多核处理器的所述多个逻辑处理分区之间逐行地有效地共享。

公开(公告)号：US08359449B2

公开(公告)日：2013-01-22

申请号：US12640733

申请日：2009-12-17

申请人： Mathew Accapadi ,  Dirk Michel ,  Bret Ronald Olszewski

发明人： Mathew Accapadi ,  Dirk Michel ,  Bret Ronald Olszewski

IPC分类号： G06F12/00

CPC分类号： G06F12/08 ,  G06F12/023 ,  G06F2212/152

摘要： A method manages memory paging operations. Responsive to a request to page out a memory page from a shared memory pool, the method identifies whether a physical space within one of a number of paging space devices has been allocated for the memory page. If physical space within the paging space device has not been allocated for the memory page, a page priority indicator for the memory page is identified. The memory page is then allocated to one of a number of memory pools within one of the number of paging space devices. The memory page is allocated one of the memory pools according to the page priority indicator of the memory page. The memory page is then written to the allocated memory pools.

摘要翻译： 一种方法管理存储器寻呼操作。 响应于从共享存储器池翻出存储器页面的请求，该方法识别是否已经为存储器页面分配了多个分页空间设备之一内的物理空间。 如果寻呼空间设备内的物理空间尚未被分配给存储器页面，则识别用于存储器页面的页面优先级指示符。 然后将存储器页面分配给多个调页空间设备之一内的多个存储器池中的一个。 根据存储器页面的页面优先级指示符，为存储器页面分配一个存储器池。 然后将内存页写入分配的内存池。

公开(公告)号：US08104036B2

公开(公告)日：2012-01-24

申请号：US12054673

申请日：2008-03-25

申请人： Bret Ronald Olszewski ,  Luc Rene Smolders ,  Mysore Sathyanarayana Srinivas

发明人： Bret Ronald Olszewski ,  Luc Rene Smolders ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F9/46

CPC分类号： G06F11/3423

摘要： In a multiprocessor system where each processor has the capacity to executing multiple hardware threads, a processor capacity monitor calculates a logical usage percentage of each of the available hardware threads. The processor capacity monitor calculates a physical usage percentage of each of the processors by each of the available threads. The processor capacity monitor calculate a percentage usage of a total capacity of the physical processors from the logical usage percentages and the physical usage percentages, such that the percentage usage reflects the actual use of the physical processors independent of which of the threads is used.

摘要翻译： 在每个处理器具有执行多个硬件线程的能力的多处理器系统中，处理器容量监视器计算每个可用硬件线程的逻辑使用百分比。 处理器容量监视器通过每个可用线程计算每个处理器的物理使用百分比。 处理器容量监视器根据逻辑使用百分比和物理使用百分比计算物理处理器总容量的百分比使用率，从而使用百分比反映了与使用哪个线程无关的物理处理器的实际使用。

公开(公告)号：US07555753B2

公开(公告)日：2009-06-30

申请号：US10787659

申请日：2004-02-26

申请人： Bret Ronald Olszewski ,  Luc Rene Smolders ,  Mysore Sathyanarayana Srinivas

发明人： Bret Ronald Olszewski ,  Luc Rene Smolders ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F9/46

CPC分类号： G06F11/3423

摘要： In a multiprocessor system where each processor has the capacity to executing multiple hardware threads, a method, system, and program for monitoring the percentage usage of the total capacity of the physical processors is provided. A processor capacity monitor calculates a logical usage percentage of each of the available hardware threads. In addition, the processor capacity monitor calculates a physical usage percentage of each of the processors by each of the available threads. Then, the processor capacity monitor multiplies the logical usage percentage and physical usage percentage for each of the threads and sums the result. The summed result is divided by the number of physical processors to determine the percentage usage of the total capacity of the physical processors.

摘要翻译： 在每个处理器具有执行多个硬件线程的能力的多处理器系统中，提供了用于监视物理处理器的总容量的百分比使用的方法，系统和程序。 处理器容量监视器计算每个可用硬件线程的逻辑使用百分比。 此外，处理器容量监视器通过每个可用线程计算每个处理器的物理使用百分比。 然后，处理器容量监视器将每个线程的逻辑使用百分比和物理使用百分比相乘，并将结果相加。 总和结果除以物理处理器的数量，以确定物理处理器总容量的使用百分比。

公开(公告)号：US07469331B2

公开(公告)日：2008-12-23

申请号：US10897329

申请日：2004-07-22

申请人： David Alan Hepkin ,  Bret Ronald Olszewski

发明人： David Alan Hepkin ,  Bret Ronald Olszewski

IPC分类号： G06F9/26

CPC分类号： G06F9/4843 ,  G06F12/109

摘要： A fork system call by a first process is detected. A second process is created as a replication of the first process with a second affinity. If a replication of the replicated shared library is present in the second affinity domain, effective addresses of the replication of the replicated shared library are mapped using a mapping mechanism of the present invention to physical addresses in the second affinity domain.

摘要翻译： 检测到第一进程的叉系统调用。 创建第二个进程作为具有第二个关联的第一个进程的复制。 如果在第二关联域中存在复制的共享库的复制，则使用本发明的映射机制将复制的共享库的复制的有效地址映射到第二关联域中的物理地址。

公开(公告)号：US06598143B1

公开(公告)日：2003-07-22

申请号：US09513819

申请日：2000-02-24

申请人： William Eugene Baker ,  Bret Ronald Olszewski ,  Jeffrey Anderson Smith ,  David Blair Whitworth

发明人： William Eugene Baker ,  Bret Ronald Olszewski ,  Jeffrey Anderson Smith ,  David Blair Whitworth

IPC分类号： G06F1200

CPC分类号： G06F12/023 ,  G06F12/0292 ,  Y10S707/99953 ,  Y10S707/99957

摘要： Initially, data is copied from a disk to a page frame and then to a read buffer, for instance. Next, a check is made to determine whether the percent of real memory occupied by file pages is less than a preset maximum volume. If so, no space is allocated for additional file page and no page frames are returned to the free list. If not, the VMM selects the best candidate file pages in real memory and returns them to the free list. Ideal candidates are a thread's memory pages, from a thread doing sequential I/O the file system. In so doing, the page frames are added to the free list as soon as the I/O is complete.

摘要翻译： 最初，例如，数据从磁盘复制到页面帧，然后复制到读取缓冲区。 接下来，进行检查以确定文件页面占用的实际内存的百分比是否小于预设的最大音量。 如果是这样，没有为额外的文件页面分配空间，并且没有页面框架返回到空闲列表。 如果没有，则VMM将选择真实内存中的最佳候选文件页面并将其返回到空闲列表。 理想的候选人是一个线程的内存页面，从线程执行顺序I / O文件系统。 一旦I / O完成，就可以将页面框架添加到空闲列表中。