公开(公告)号：US08179946B2

公开(公告)日：2012-05-15

申请号：US12274551

申请日：2008-11-20

申请人： Brian Lee Roberts ,  Kenneth C Grobaski ,  Anand P Narayan

发明人： Brian Lee Roberts ,  Kenneth C Grobaski ,  Anand P Narayan

IPC分类号： H04B1/00

CPC分类号： H04B1/7117

摘要： A controller for advanced receivers configures a plurality of advanced receiver modules based on figures of merit computed on the input signal. The controller also selects the appropriate output signal based on figures of merit of either the input or the output signals. The controller decisions can also be made in a bursty manner, where only a subset of the decisions to be made are made at a given time, thereby limiting the processing load of the control processor.

摘要翻译： 用于高级接收器的控制器基于在输入信号上计算的品质因数配置多个高级接收器模块。 控制器还根据输入或输出信号的品质因数选择合适的输出信号。 控制器决定还可以以突发方式进行，其中仅在给定时间做出要作出的决定的子集，从而限制控制处理器的处理负担。

公开(公告)号：US08514910B2

公开(公告)日：2013-08-20

申请号：US13462238

申请日：2012-05-02

申请人： Brian Lee Roberts ,  Kenneth C Grobaski ,  Anand P Narayan

发明人： Brian Lee Roberts ,  Kenneth C Grobaski ,  Anand P Narayan

IPC分类号： H04B1/711

CPC分类号： H04B1/7117

摘要： A controller for advanced receivers configures a plurality of advanced receiver modules based on figures of merit computed on the input signal. The controller also selects the appropriate output signal based on figures of merit of either the input or the output signals. The controller decisions can also be made in a bursty manner, where only a subset of the decisions to be made are made at a given time, thereby limiting the processing load of the control processor.

摘要翻译： 用于高级接收器的控制器基于在输入信号上计算的品质因数配置多个高级接收器模块。 控制器还根据输入或输出信号的品质因数选择合适的输出信号。 控制器决定还可以以突发方式进行，其中仅在给定时间做出要作出的决定的子集，从而限制控制处理器的处理负担。

公开(公告)号：US08005128B1

公开(公告)日：2011-08-23

申请号：US11893707

申请日：2007-08-17

申请人： Gagandeep Singh Lamba ,  Tommy Guess ,  Michael McCloud ,  Anand P Narayan

发明人： Gagandeep Singh Lamba ,  Tommy Guess ,  Michael McCloud ,  Anand P Narayan

IPC分类号： H04B1/00

CPC分类号： H04B1/71072 ,  H04B1/7097 ,  H04B1/7107 ,  H04B1/71075 ,  H04B1/7115 ,  H04B1/7117 ,  H04B15/00 ,  H04B2001/71077 ,  H04B2201/709718 ,  H04J13/00 ,  H04J13/0048 ,  H04L43/08 ,  H04W24/08

摘要： A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the subchannel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal.

摘要翻译： CDMA系统中的接收机包括每个源产生组合信号的前端处理器。 符号估计器处理组合信号以产生符号估计。 S矩阵生成模块基于子信道符号估计来精化这些符号估计。 一个干扰消除器被配置为消除来自多个接收信号中的至少一个的干扰，用于产生至少一个干扰消除信号。

公开(公告)号：US07697595B2

公开(公告)日：2010-04-13

申请号：US11432580

申请日：2006-05-11

申请人： Vijay Nagarajan ,  Louis L Scharf ,  Anand P Narayan

发明人： Vijay Nagarajan ,  Louis L Scharf ,  Anand P Narayan

IPC分类号： H04B1/69

CPC分类号： H04B1/7107 ,  H04B1/712 ,  H04B2201/70703 ,  H04B2201/709727

摘要： A receiver employs low-rate processing to synthesize the effect of high-rate interference in a received multi-rate signal. Each high-rate subchannel is analyzed on its low-rate descendents to produce symbol estimates for each low-rate symbol interval. The symbol estimates are applied to low-rate descendent subchannels, which are then combined to synthesize the effects of the high-rate interference. An interference canceller processes the synthesized interference with the received signal for producing an interference-cancelled signal. Alternatively, analogous steps may be applied at high-rate to analyze, synthesize, and cancel the effects of low-rate interference in a multi-rate signal.

摘要翻译： 接收机采用低速率处理来合成接收的多速率信号中的高速率干扰的影响。 在其低速率后代分析每个高速率子信道，以对每个低速率符号间隔产生符号估计。 符号估计适用于低速率后代子信道，然后将其合并，以合成高速率干扰的影响。 干扰消除器处理与接收信号的合成干扰以产生干扰消除信号。 或者，可以以高速率应用类似的步骤来分析，合成和消除多速率信号中的低速率干扰的影响。

公开(公告)号：US08085889B1

公开(公告)日：2011-12-27

申请号：US11858074

申请日：2007-09-19

申请人： Anand P Narayan ,  Greg Graham ,  David R Meyer ,  Prashant Jain

发明人： Anand P Narayan ,  Greg Graham ,  David R Meyer ,  Prashant Jain

IPC分类号： H03D1/04

CPC分类号： H04B1/7097 ,  G01S5/0215 ,  G01S5/10 ,  G01S19/22 ,  H04B1/7093 ,  H04B1/7105 ,  H04B1/7117 ,  H04B2001/70935 ,  H04B2201/70701 ,  H04B2201/70715

摘要： An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

摘要翻译： 干扰消除接收机在对准发射机定时之后组合来自多个路径的数据，并且使用均衡器或Rake接收机来计算符号估计。 从符号估计产生干扰估计，并且在将干扰估计重新对准接收机定时之后组合多个干扰估计。 对干扰消除数据的每个段计算符号估计的至少两个段。 可以采用各种技术来控制这些操作的等待时间和顺序，并且消除器内的子系统可以使用不同的处理时钟速度。