Support for out-of-order execution of loads and stores in a processor
    1.
    发明授权
    Support for out-of-order execution of loads and stores in a processor 失效
    支持处理器中负载和存储的无序执行

    公开(公告)号:US5931957A

    公开(公告)日:1999-08-03

    申请号:US829669

    申请日:1997-03-31

    摘要: To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.

    摘要翻译: 为了支持关于存储指令执行无序的加载指令,实现了一种机制来检测(和校正)在逻辑上先前的存储指令之前执行的加载指令的发生,并且其中加载指令接收数据为 由存储指令修改之前的位置,以及加载指令的正确数据,包括来自存储指令的字节。 另外,为了执行与加载指令无序的存储指令,实现了一种机制来保持存储指令不会破坏由逻辑上较早的加载指令使用的数据。 此外,为了支持相对于彼此执行的无序执行的加载指令,实现一种机制以确保任何一对加载指令(其访问至少一个共同的字节)返回数据与执行加载指令一致 为了。