公开(公告)号：US06484230B1

公开(公告)日：2002-11-19

申请号：US09161640

申请日：1998-09-28

申请人： Brian R. Konigsburg ,  Alexander Edward Okpisz ,  Thomas Albert Petersen ,  Bruce Joseph Ronchetti

发明人： Brian R. Konigsburg ,  Alexander Edward Okpisz ,  Thomas Albert Petersen ,  Bruce Joseph Ronchetti

IPC分类号： G06F1300

CPC分类号： G06F12/0831

摘要： A method and system of facilitating storage accesses within a multiprocessor system subsequent to a synchronization instruction by a local processor consists of determining if data for the storage accesses is cacheable and if there is a “hit” in a cache. If both conditions are met, the storage accesses return the data to the local processor. The storage accesses have an entry on an interrupt table which is used to discard the returned data if a snoop kills the line before the synchronization instruction completes. After the cache returns data, a return data bit is set in the interrupt table. A snoop killing the line sets a snooped bit in the interrupt table. Upon completion of the synchronization instruction, any entries in the interrupt table subsequent to the synchronization instruction that have the return data bit and snooped bit set are flushed. The flush occurs because the data returned to the local processor due to a “cacheable hit” subsequent to the synchronization instruction was out of order with the snoop and the processor must flush the data and go back out to the system bus for the new data.

摘要翻译： 在本地处理器的同步指令之后，便于在多处理器系统内存储访问的方法和系统包括确定用于存储访问的数据是否可高速缓存以及高速缓存中是否存在“命中”。 如果满足这两个条件，存储访问将数据返回到本地处理器。 存储访问在中断表上有一个条目，如果在同步指令完成之前窥探杀死了该行，则该条目用于丢弃返回的数据。 缓存返回数据后，在中断表中设置返回数据位。 一个窥探杀死线路在中断表中设置一个窥探的位。 完成同步指令之后，刷新具有返回数据位和被监听位置位的同步指令之后的中断表中的任何条目。 发生冲突是因为由于在同步指令之后的“可缓存命中”返回到本地处理器的数据与snoop不一致，并且处理器必须刷新数据并返回到系统总线以获取新数据。

公开(公告)号：US6021467A

公开(公告)日：2000-02-01

申请号：US713056

申请日：1996-09-12

申请人： Brian R. Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

发明人： Brian R. Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F12/0859 ,  G06F12/0897 ,  Y02B60/1225

摘要： An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request. The present invention reduces the number of accesses to the level two cache and allows data requests to be satisfied in parallel versus serially when multiple successive level one cache misses occur.

摘要翻译： 一种用于处理信息处理系统中的多个高速缓存未命中到单个高速缓存行的装置和方法，该信息处理系统包括用于存储不在一级高速缓存中的数据的请求的未命中队列，以及比较器，用于将存储在所述未命中队列中的数据的请求与 确定是否存在针对二级缓存的同一高速缓存行中的数据的多个请求。 来自与二级缓存相同的高速缓存行的数据的新请求作为旧队列中的数据的较早原始请求被标记为加载命中重新加载。 标记为加载命中重载的请求随后与匹配的原始请求分组在一起并一起转发到二级缓存，其中原始请求请求来自二级缓存的数据。 加载命中重新加载请求不访问二级缓存，而是通过从匹配的原始请求的二级缓存输出的高速缓存行中提取数据来绕过二级缓存的访问。 本发明减少对二级高速缓存的访问次数，并且允许当发生多个连续一级高速缓存未命中时并行地对数据请求进行满足。

公开(公告)号：US5805849A

公开(公告)日：1998-09-08

申请号：US829592

申请日：1997-03-31

申请人： Paul Joseph Jordan ,  Brian R. Konigsburg ,  Hung Qui Le ,  Steven Wayne White

发明人： Paul Joseph Jordan ,  Brian R. Konigsburg ,  Hung Qui Le ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/3857

摘要： A data processor assigns a unique identifier to each instruction. As there are a finite number of unique identifiers, the identifiers are reused during execution of a program within the data processing system. To maintain an age relationship between instructions executing in the pipeline processor, a methodology is developed to ensure that reused identifiers are properly designated as being younger than their older but larger in magnitude, counterparts. To resolve this issue, assume that the identifier assigned to each instruction has N bits, and therefore, there are 2.sup.N identifiers to be assigned to instructions in the program. The 2.sup.N identifiers are separated into 2.sup.m banks. In addition to assigning identifiers to each instruction, an identifier assignment logic circuit within the pipeline processor provides a global signal that indicates which bank is a youngest bank from which the identifiers are assigned to a remaining portion of the pipeline processor. The global signal preconditions portions of the two identifiers being compared. Subsequently, a result of this conditioning is concatenated with a remaining portion of a selected identifier. The modification of the upper bits of the identifier maintains a relative age position for the identifiers and their associated instructions in the pipelined processor.

摘要翻译： 数据处理器为每个指令分配唯一的标识符。 由于存在有限数量的唯一标识符，所以在数据处理系统内的程序执行期间重新使用标识符。 为了保持在流水线处理器中执行的指令之间的年龄关系，开发了一种方法，以确保重复使用的标识符被正确地指定为年龄小于较大的，较大的数量。 为了解决这个问题，假定分配给每个指令的标识符具有N位，因此，有2N个标识符被分配给程序中的指令。 2N个标识符分成2m个银行。 除了为每个指令分配标识符之外，流水线处理器内的标识符分配逻辑电路提供一个全局信号，其指示哪个存储体是最小的存储体，其中标识符从其被分配给流水线处理器的剩余部分。 两个标识符的全局信号前提条件部分被比较。 随后，这种调理的结果与所选标识符的剩余部分连接。 标识符的高位的修改保持流水线处理器中的标识符及其相关联的指令的相对年龄位置。

公开(公告)号：US5802571A

公开(公告)日：1998-09-01

申请号：US734318

申请日：1996-10-21

申请人： Brian R. Konigsburg ,  John Stephen Muhich ,  Steven Wayne White

发明人： Brian R. Konigsburg ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F12/12 ,  G06F12/08

CPC分类号： G06F12/0859

摘要： An age-based arbitration scheme for enforcing data coherency in an information handling system is disclosed. As loads and stores access a cache, if a cache miss occurs, a miss request is generated and tagged with the cycle or age in which the miss is detected. If a castout is required, it is also tagged with the cycle in which the load or store access occurred, and the line being replaced or cast out is marked as being invalid in that level of hierarchy. The arbitration rules for the next level of memory hierarchy are defined such that all requests that are generated during a particular cycle are given priority over all of the requests generated during any subsequent cycle. As a result, if a load miss occurs for a cache line which is present in the castout buffer, the castout request tagged with an earlier age will be arbitrated into the next memory hierarchy level prior to the arrival of the newly generated miss requests. The age-based arbitration scheme can also be used for multiple cache accesses occurring in parallel.

摘要翻译： 公开了一种用于在信息处理系统中执行数据一致性的基于年龄的仲裁方案。 当加载和存储访问缓存时，如果发生高速缓存未命中，则会生成错误请求并标记检测到未命中的周期或年龄。 如果需要castout，它也会被标记为发生加载或存储访问的循环，并且被替换或丢弃的行在该级别的级别中被标记为无效。 定义下一级存储器层级的仲裁规则，使得在特定周期期间生成的所有请求优先于在任何后续周期期间生成的所有请求。 结果，如果对于存在于转储缓冲器中的高速缓存行发生负载缺失，则在新生成的未命中请求到达之前，具有较早年龄的标记的转换请求将被仲裁到下一个存储器层级中。 基于年龄的仲裁方案也可以用于并行发生的多个高速缓存访​​问。

公开(公告)号：US20220407675A1

公开(公告)日：2022-12-22

申请号：US17350758

申请日：2021-06-17

申请人： BRIAN R. KONIGSBURG

发明人： BRIAN R. KONIGSBURG

IPC分类号： H04L7/00

摘要： In an example, a synchronization signal can be transmitted to a plurality of synchronizers. The plurality of synchronizers can include a plurality of upstream synchronizers and a downstream synchronizer. Each synchronizer of the plurality of upstream synchronizers can be caused to count from a respective count value until a predetermined end count sequence value in response to receiving the synchronization signal. The respective count value stored at each synchronizer can be representative of a difference in time between a respective upstream synchronizer of the plurality of upstream synchronizers receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal. A respective processing element of a plurality of processing elements can be caused to start a respective function or operation in response to a respective upstream synchronizer reaching the predetermined end count sequence value.

公开(公告)号：US20110314259A1

公开(公告)日：2011-12-22

申请号：US12817609

申请日：2010-06-17

申请人： Kattamuri Ekanadham ,  Brian R. Konigsburg ,  David S. Levitan ,  Jose E. Moreira ,  David Mui ,  IL Park

发明人： Kattamuri Ekanadham ,  Brian R. Konigsburg ,  David S. Levitan ,  Jose E. Moreira ,  David Mui ,  IL Park

IPC分类号： G06F9/30

CPC分类号： G06F9/30 ,  G06F9/30134 ,  G06F9/30163 ,  G06F9/3861

摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.

摘要翻译： 一个指针用于指向一堆信息中的下一个读取位置。 将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。 为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

公开(公告)号：US20080276080A1

公开(公告)日：2008-11-06

申请号：US12171370

申请日：2008-07-11

申请人： Brian R. Konigsburg ,  David Stephen Levitan ,  Wolfram M. Sauer ,  Samuel Jonathan Thomas

发明人： Brian R. Konigsburg ,  David Stephen Levitan ,  Wolfram M. Sauer ,  Samuel Jonathan Thomas

IPC分类号： G06F9/38 ,  G06F9/44

CPC分类号： G06F9/3806

摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.

摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。

公开(公告)号：US06279105B1

公开(公告)日：2001-08-21

申请号：US09173039

申请日：1998-10-15

申请人： Brian R. Konigsburg ,  David Stephen Levitan

发明人： Brian R. Konigsburg ,  David Stephen Levitan

IPC分类号： G06F1300

CPC分类号： G06F9/3806 ,  G06F9/3836 ,  G06F9/3861

摘要： In a branch instruction target address cache, an entry associated with a fetched block of instructions includes a target address of a branch instruction residing in the next sequential block of instructions. The entry will include a sequential address associated with the branch instruction and a prediction of whether the target address is taken or not taken.

摘要翻译： 在分支指令目标地址高速缓存中，与获取的指令块相关联的条目包括驻留在下一个顺序指令块中的分支指令的目标地址。 条目将包括与分支指令相关联的顺序地址以及是否采取目标地址的预测。

公开(公告)号：US08943301B2

公开(公告)日：2015-01-27

申请号：US13101650

申请日：2011-05-05

申请人： Brian R. Konigsburg ,  David Stephen Levitan ,  Wolfram M. Sauer ,  Samuel Jonathan Thomas

发明人： Brian R. Konigsburg ,  David Stephen Levitan ,  Wolfram M. Sauer ,  Samuel Jonathan Thomas

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38

CPC分类号： G06F9/3806

摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.

摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。

公开(公告)号：US07487334B2

公开(公告)日：2009-02-03

申请号：US11050350

申请日：2005-02-03

申请人： Brian R. Konigsburg ,  Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

发明人： Brian R. Konigsburg ,  Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

IPC分类号： G06F9/34

CPC分类号： G06F9/322 ,  G06F9/382

摘要： Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch prior to writing the branch into a Level 1 (L1) cache to provide a pre-decoded branch, and then writing the pre-decoded branch into the L1 cache. By pre-calculating matters relating to the targets of branches before the branches are written into the L1 cache, for example, by re-encoding relative branches as absolute branches, a reduction in branch redirect delay can be achieved, thus providing a substantial improvement in overall processor performance.

摘要翻译： 用于确定数据处理系统中分支目标的方法，系统和计算机程序产品。 一种用于确定数据处理系统中的分支的目标的方法包括在将分支写入级别1（L1）高速缓存之前执行与确定分支的目标有关的至少一个预计算，以提供预解码分支 ，然后将预解码的分支写入L1高速缓存。 通过在将分支写入L1高速缓存之前预先计算与分支目标相关的事项，例如通过将相关分支重新编码为绝对分支，可以实现分支重定向延迟的减少，从而提供了显着的改进 整体处理器性能。