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    Generating different delay ratios for a strobe delay
    1.
    发明授权
    Generating different delay ratios for a strobe delay 有权
    为选通延迟生成不同的延迟比

    公开(公告)号：US07109767B1

    公开(公告)日：2006-09-19

    申请号：US10889610

    申请日：2004-07-12

    申请人： Brian W. Amick ,  Aparna Ramachandran ,  Dong J. Yoon ,  Tri K. Tran ,  Gajendra P. Singh ,  Claude R. Gauthier

    发明人： Brian W. Amick ,  Aparna Ramachandran ,  Dong J. Yoon ,  Tri K. Tran ,  Gajendra P. Singh ,  Claude R. Gauthier

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0805 ,  H03L7/085

    摘要： A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.

    摘要翻译： 与典型的寄存器控制的延迟锁定环（RDLL）相比，已经发现数字延迟锁定环路具有减小的面积，用于控制对驱动异步FIFO的选通信号提供延迟的选通延迟线。 该结果通过减少RDLL的比率计算（即齿轮逻辑）电路来实现。 主延迟线接收一个控制码，将参考时钟延迟一个时钟周期。 从属延迟线接收控制码，以将选通信号延迟预定分钟的时钟周期。 主延迟线可以包括响应于控制代码的各个部分，其有效地将信号延迟了时钟周期的一部分，该延迟具有与从属延迟线的各个部分相关联的延迟的固定关系。

    Power and area efficient SerDes transmitter
    3.
    发明授权
    Power and area efficient SerDes transmitter 有权
    电源和区域高效的SerDes变送器

    公开(公告)号：US08542764B2

    公开(公告)日：2013-09-24

    申请号：US12353717

    申请日：2009-01-14

    申请人： Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

    发明人： Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

    IPC分类号： H04L27/00

    CPC分类号： H03M9/00 ,  H03K3/00 ,  H03L7/0814

    摘要： A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from another group of data. The SerDes transmitter can further comprise an analog block operating in an analog voltage domain. The analog block can be configured to receive the first group of bits of data from the digital block, receive the history bits from the digital block, generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits, align each combination of bits to a phase of a multi-phase clock; and input each combination into an output driver.

    摘要翻译： 一种系统和方法包括一个SerDes发射机，其包括以数字电压域工作的数字模块。 数字块可以被配置为并行地接收数据的第一组数据并存储来自另一组数据的历史比特。 SerDes发射机还可以包括在模拟电压域中工作的模拟块。 模拟块可以被配置为从数字块接收第一组数据，从数字块接收历史比特，从第一比特组生成具有一个或多个比特的比特的多个组合， 来自历史比特的更多比特，将每个比特组合对齐到多相时钟的相位; 并将每个组合输入到输出驱动器中。

    Power and Area Efficient SerDes Transmitter
    5.
    发明申请
    Power and Area Efficient SerDes Transmitter 有权
    电源和区域效率SerDes变送器

    公开(公告)号：US20100177841A1

    公开(公告)日：2010-07-15

    申请号：US12353717

    申请日：2009-01-14

    申请人： Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

    发明人： Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

    IPC分类号： H04L27/00

    CPC分类号： H03M9/00 ,  H03K3/00 ,  H03L7/0814

    摘要： A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from another group of data. The SerDes transmitter can further comprise an analog block operating in an analog voltage domain. The analog block can be configured to receive the first group of bits of data from the digital block, receive the history bits from the digital block, generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits, align each combination of bits to a phase of a multi-phase clock; and input each combination into an output driver.

    摘要翻译： 一种系统和方法包括一个SerDes发射机，其包括以数字电压域工作的数字模块。 数字块可以被配置为并行地接收数据的第一组数据并存储来自另一组数据的历史比特。 SerDes发射机还可以包括在模拟电压域中工作的模拟块。 模拟块可以被配置为从数字块接收第一组数据，从数字块接收历史比特，从第一比特组生成具有一个或多个比特的比特的多个组合， 来自历史比特的更多比特，将每个比特组合对齐到多相时钟的相位; 并将每个组合输入到输出驱动器中。