公开(公告)号：US07193447B1

公开(公告)日：2007-03-20

申请号：US10839941

申请日：2004-05-06

申请人： Shao H. Liu ,  Tri K. Tran ,  Brian W. Amick

发明人： Shao H. Liu ,  Tri K. Tran ,  Brian W. Amick

IPC分类号： G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC分类号： G11C7/065 ,  G11C7/12 ,  H03F3/45632 ,  H03F2203/45212 ,  H03F2203/45681

摘要： A sense amplifier latch that is operable to interface with high common-mode input voltages with wide ranges for all process variations. The sense amplifier latch comprises a cross-coupled latch having first and second rail signals; a pre-charge device; an equalization device; pass devices for enabling input devices to receive pad and reference inputs. In the present invention, the input devices comprise push-pull impedance dividers are used to preserve the input difference voltage while dramatically lowering the common-mode output voltage. The outputs of the impedance dividers are fed to the cross-coupled latch of the sense amplifier using n-channel pass gates.

摘要翻译： 读出放大器锁存器，用于与所有过程变化的宽范围内的高共模输入电压接口。 读出放大器锁存器包括具有第一和第二轨道信号的交叉耦合锁存器; 预充电设备; 均衡装置; 允许输入设备接收焊盘和参考输入。 在本发明中，输入装置包括推挽阻抗分配器用于保持输入差分电压，同时显着降低共模输出电压。 阻抗分配器的输出端使用n沟道栅极馈送到读出放大器的交叉耦合锁存器。

公开(公告)号：US06774665B2

公开(公告)日：2004-08-10

申请号：US10255341

申请日：2002-09-26

申请人： Brian W. Amick ,  Lynn A. Warriner ,  Claude R. Gauthier ,  Tri K. Tran

发明人： Brian W. Amick ,  Lynn A. Warriner ,  Claude R. Gauthier ,  Tri K. Tran

IPC分类号： H03K1716

CPC分类号： H03K19/00384 ,  H03K19/018507

摘要： A cascode SSTL output buffer using a source follower circuit includes a biasing circuit arranged to generate a first bias signal. The source follower circuit is responsive to the first bias signal and generates a second bias signal which is then used by a cascode circuit that receives an input signal to the SSTL output buffer to drive an output signal from the SSTL output buffer.

摘要翻译： 使用源极跟随器电路的共源共栅SSTL输出缓冲器包括被配置为产生第一偏置信号的偏置电路。 源极跟随器电路响应于第一偏置信号并产生第二偏置信号，然后由共源共栅电路使用该信号，其接收到SSTL输出缓冲器的输入信号以驱动来自SSTL输出缓冲器的输出信号。

公开(公告)号：US06784690B2

公开(公告)日：2004-08-31

申请号：US10234657

申请日：2002-09-04

申请人： Tri K. Tran ,  Cong K. Khieu

发明人： Tri K. Tran ,  Cong K. Khieu

IPC分类号： H03K1716

CPC分类号： H03K19/0005 ,  H03K17/167

摘要： Disclosed is an input/output (IO) device having a power supply node, an input node for receiving an input data signal, and an output node for outputting an output data signal generated in response to the input node receiving the input data bit signal. The IO device also includes a pull-up driver coupled to the power supply node and the output node, wherein the pull-up driver comprises an impedance at the output node which is constant for all voltages at the output node. Additionally, the IO device may have a circuit coupled to the input node, the pull-up driver, and the output node. This circuit is configured to generate a signal that is provided to the pull-up driver. The signal generated by the circuit varies as a function of the voltage at the output node.

摘要翻译： 公开了具有电源节点，用于接收输入数据信号的输入节点和用于输出响应于输入节点接收输入数据位信号而生成的输出数据信号的输出/输出（IO）装置。 IO设备还包括耦合到电源节点和输出节点的上拉驱动器，其中上拉驱动器包括在输出节点处对于输出节点处的所有电压是恒定的阻抗。 另外，IO设备可以具有耦合到输入节点，上拉驱动器和输出节点的电路。 该电路被配置为产生提供给上拉驱动器的信号。 由电路产生的信号作为输出节点处的电压的函数而变化。

公开(公告)号：US07109767B1

公开(公告)日：2006-09-19

申请号：US10889610

申请日：2004-07-12

申请人： Brian W. Amick ,  Aparna Ramachandran ,  Dong J. Yoon ,  Tri K. Tran ,  Gajendra P. Singh ,  Claude R. Gauthier

发明人： Brian W. Amick ,  Aparna Ramachandran ,  Dong J. Yoon ,  Tri K. Tran ,  Gajendra P. Singh ,  Claude R. Gauthier

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805 ,  H03L7/085

摘要： A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.

摘要翻译： 与典型的寄存器控制的延迟锁定环（RDLL）相比，已经发现数字延迟锁定环路具有减小的面积，用于控制对驱动异步FIFO的选通信号提供延迟的选通延迟线。 该结果通过减少RDLL的比率计算（即齿轮逻辑）电路来实现。 主延迟线接收一个控制码，将参考时钟延迟一个时钟周期。 从属延迟线接收控制码，以将选通信号延迟预定分钟的时钟周期。 主延迟线可以包括响应于控制代码的各个部分，其有效地将信号延迟了时钟周期的一部分，该延迟具有与从属延迟线的各个部分相关联的延迟的固定关系。