公开(公告)号：US20230300497A1

公开(公告)日：2023-09-21

申请号：US17999693

申请日：2021-05-24

申请人： BRILLNICS SINGAPORE PTE. LTD.

发明人： Masayuki UNO ,  Rimon IKENO ,  Ken MIYAUCHI ,  Kazuya MORI ,  Hideki OWADA

IPC分类号： H04N25/78 ,  H04N25/77

CPC分类号： H04N25/78 ,  H04N25/77

摘要： Some embodiments relate to an imaging system including an active pixel a comparator, a write control circuit, and an analog-to-digital conversion (ADC) memory. The active pixel may include a photodiode and a plurality of transistors. The comparator may be operative coupled to the active pixel and configured to receive an output of the active pixel. The write control circuit may be operative coupled to the comparator and configured to receive an output from the comparator. The ADC memory may be operatively coupled to the write control circuit. A data structure may be stored in the ADC memory, and may be configured to store at least a first data string, which may include a set of flag bits for identifying each ADC operation performed and a set of ADC data bits.

公开(公告)号：US20230300493A1

公开(公告)日：2023-09-21

申请号：US17999690

申请日：2021-05-24

申请人： BRILLNICS SINGAPORE PTE. LTD.

发明人： Masayuki UNO ,  Rimon IKENO ,  Ken MIYAUCHI ,  Kazuya MORI ,  Hideki OWADA

IPC分类号： H04N5/225

CPC分类号： H04N25/77

摘要： Some embodiments relate to an active pixel for use in a digital pixel sensor (DPS) imaging system having complete intra-pixel charge transfer functionality. The active pixel may include a first photodiode, and a first transfer gate and a second transfer gate each operatively coupled to the first photodiode. The first transfer gate and the second transfer gate may reside at opposite sides of the first photodiode. An electron drift current within the first photodiode may cause two direction charge transfer of charge of the first photodiode to the first transfer gate and the second transfer gate.

公开(公告)号：US20230239594A1

公开(公告)日：2023-07-27

申请号：US17999682

申请日：2021-05-24

申请人： BRILLNICS SINGAPORE PTE. LTD.

发明人： Masayuki UNO ,  Rimon IKENO ,  Ken MIYAUCHI ,  Kazuya MORI ,  Hideki OWADA

IPC分类号： H04N25/772 ,  H01L27/146

CPC分类号： H04N25/772 ,  H01L27/14612

摘要： Some embodiments relate to an imaging system including an active pixel and an analog-to-digital conversion (ADC) circuit including comparator. The comparator may be operatively coupled to the active pixel and configured to receive an output of the active pixel. The back-end ADC and memory circuit may be operatively coupled to the active pixel. The back-end ADC and memory circuit may include a write control circuit, an ADC memory operatively coupled to a read/write data bus and to the write control circuit, and a state latch operatively coupled to the write control circuit.

公开(公告)号：US20220132067A1

公开(公告)日：2022-04-28

申请号：US17510891

申请日：2021-10-26

申请人： Brillnics Singapore Pte. Ltd.

发明人： Kazuya MORI ,  Masayuki UNO ,  Hideki OWADA

IPC分类号： H04N5/378 ,  H04N5/3745 ,  H04N5/357 ,  H04N5/351

摘要： A photoelectric conversion reading part of a pixel includes a photoelectric conversion element for storing therein, in a storing period, charges generated by the photoelectric conversion, a transfer element for transferring, in a transfer period following the storing period, the charges stored in the photoelectric conversion element, an output node to which the charges stored in the photoelectric conversion element are transferred through the transfer element, a reset element for resetting, in a reset period, the output node to a predetermined potential, an output buffer part for converting the charges in the output node into a voltage signal at a level determined by the amount of the charges and outputting the voltage signal as the pixel signal, and an output voltage control part for controlling an output signal level of the pixel signal from the output buffer part to a controlled level determined by the operational state.