公开(公告)号：US20030097498A1

公开(公告)日：2003-05-22

申请号：US10269666

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Barton J. Sano ,  Koray Oner ,  Laurent R. Moll ,  Manu Gulati

IPC: G06F013/28

CPC classification number: H04L49/10 ,  H04L49/602

Abstract: An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

Abstract translation: 一种装置包括第一接口电路，第二接口电路，用于配置为与存储器接口的存储器控​​制器和分组DMA电路。 第一接口电路被配置为耦合到用于接收和发送分组数据的第一接口。 类似地，第二接口电路被配置为耦合到用于接收和发送分组数据的第二接口。 分组DMA电路被耦合以从第一接口电路接收第一分组，并从第二接口电路接收第二分组。 分组DMA电路被配置为以写入命令将第一分组和第二分组发送到存储器控制器以写入存储器。 在一些实施例中，开关耦合到第一接口电路，第二接口电路和分组DMA电路。

公开(公告)号：US20030097416A1

公开(公告)日：2003-05-22

申请号：US10270029

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC: G06F015/167

CPC classification number: H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Abstract translation: 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些一致性命令来在互连上启动相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。