公开(公告)号：US20030217234A1

公开(公告)日：2003-11-20

申请号：US10270480

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Joseph B. Rowlands

IPC: G06F012/00

CPC classification number: G06F12/0817 ,  Y10S707/99952

Abstract: A system comprises a plurality of nodes, each node comprising one or more coherent agents coupled to an interconnect. Ownership of a coherency block accessed by a transaction on the interconnect is transferred responsive to transmission of the address on the interconnect. The system further includes a second interconnect to which the plurality of nodes are coupled, wherein ownership of a coherency block is transferred on the second interconnect responsive to a transmission of the data comprising the coherency block on the second interconnect. A first node of the plurality of nodes issues a coherency command on the second interconnect to fetch the coherency block in response to the transaction on the interconnect within the first node, whereby ownership transfers within the first node prior to ownership transferring from another one of the plurality of nodes to the first node.

Abstract translation: 系统包括多个节点，每个节点包括耦合到互连的一个或多个相干代理。 响应于互连上的地址的传输，传送由互连上的事务访问的一致性块的所有权。 该系统还包括多个节点耦合到的第二互连，其中响应于包括第二互连上的一致性块的数据的传输，在第二互连上传送一致性块的所有权。 所述多个节点中的第一节点在所述第二互连上发出相关命令以便响应于所述第一节点内的所述互连上的事务来获取所述一致性块，由此所有权转移在所述第一节点之内，从所述转移中的另一个 多个节点到第一个节点。

公开(公告)号：US20030217233A1

公开(公告)日：2003-11-20

申请号：US10269827

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Joseph B. Rowlands ,  James B. Keller

IPC: G06F012/00

CPC classification number: G06F12/0817 ,  Y10S707/99952

Abstract: A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total number of the coherency blocks in the memory. The directory is configured to allocate a first entry to track the state of the first coherency block responsive to the coherency command. If the first entry is currently tracking the state of a second coherency block, the second node is configured to generate one or more coherency commands to invalidate the second coherency block in a plurality of nodes.

Abstract translation: 耦合节点以接收相关命令并耦合到存储器，其中节点包括被配置为跟踪小于存储器中的一致性块的总数的第一数量的一致性块的状态的目录。 该目录被配置为响应于一致性命令来分配第一条目以跟踪第一一致性块的状态。 如果第一条目当前正在跟踪第二相关性块的状态，则第二节点被配置为生成一个或多个一致性命令以使多个节点中的第二一致性块无效。

公开(公告)号：US20030105828A1

公开(公告)日：2003-06-05

申请号：US10269922

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Barton J. Sano ,  Joseph B. Rowlands ,  Laurent R. Moll ,  Manu Gulati

IPC: G06F013/28 ,  G06F015/167

CPC classification number: G06F13/4022

Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Abstract translation: 装置可以包括第一系统和第二系统。 第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个被配置为耦合到单独的接口。 第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。 第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。 第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。

公开(公告)号：US20030097416A1

公开(公告)日：2003-05-22

申请号：US10270029

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC: G06F015/167

CPC classification number: H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Abstract translation: 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些一致性命令来在互连上启动相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US20030217236A1

公开(公告)日：2003-11-20

申请号：US10269828

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Joseph B. Rowlands

IPC: G06F012/00

CPC classification number: G06F12/0817 ,  Y10S707/99952

Abstract: A first node includes a first cache and a plurality of coherent agents. In response to a transaction to a coherency block by a first coherent agent of the plurality of coherent agents, the first node is configured to fetch the coherency block from another node. The other node is configured to record a state in which the coherency block is provided to the first node. The first cache is designated to store the state of the coherency block recorded by the first node.

Abstract translation: 第一节点包括第一高速缓存和多个相干代理。 响应于由多个相干代理的第一相干代理对一致性块的事务，第一节点被配置为从另一个节点获取一致性块。 另一个节点被配置为记录向第一节点提供一致性块的状态。 第一缓存被指定为存储由第一节点记录的一致性块的状态。

公开(公告)号：US20030217216A1

公开(公告)日：2003-11-20

申请号：US10270028

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Joseph B. Rowlands

IPC: G06F013/14 ,  G06F009/44

CPC classification number: G06F13/4027 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F12/082 ,  G06F2212/2542

Abstract: A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.

Abstract translation: 节点包括至少互连，耦合到互连的一个或多个相干代理以及耦合到互连的存储器桥。 内存桥被配置为保持代表其他节点的互连上的一致性。 在一个实施例中，互连不允许重试在其上启动的事务，并且存储器桥被配置为基于由其他节点中的事务访问的一致性块的状态在事务的响应阶段期间提供响应。 在另一个实施例中，节点还包括多个接口电路和开关。 多个接口电路中的每一个被配置为耦合到接口以从其他节点接收相干命令。 开关被配置为选择性地将多个接口电路耦合到存储器桥以将相干命令传送到存储器桥。

公开(公告)号：US20030191894A1

公开(公告)日：2003-10-09

申请号：US10394132

申请日：2003-03-21

Applicant: Broadcom Corp

Inventor： Mark D. Hayter ,  Joseph B. Rowlands

IPC: G06F012/00

CPC classification number: G06F12/0888

Abstract: A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication.