公开(公告)号：US20030217233A1

公开(公告)日：2003-11-20

申请号：US10269827

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Joseph B. Rowlands ,  James B. Keller

IPC: G06F012/00

CPC classification number: G06F12/0817 ,  Y10S707/99952

Abstract: A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total number of the coherency blocks in the memory. The directory is configured to allocate a first entry to track the state of the first coherency block responsive to the coherency command. If the first entry is currently tracking the state of a second coherency block, the second node is configured to generate one or more coherency commands to invalidate the second coherency block in a plurality of nodes.

Abstract translation: 耦合节点以接收相关命令并耦合到存储器，其中节点包括被配置为跟踪小于存储器中的一致性块的总数的第一数量的一致性块的状态的目录。 该目录被配置为响应于一致性命令来分配第一条目以跟踪第一一致性块的状态。 如果第一条目当前正在跟踪第二相关性块的状态，则第二节点被配置为生成一个或多个一致性命令以使多个节点中的第二一致性块无效。

公开(公告)号：US20030097416A1

公开(公告)日：2003-05-22

申请号：US10270029

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC: G06F015/167

CPC classification number: H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Abstract translation: 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些一致性命令来在互连上启动相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。