公开(公告)号：US20170278582A1

公开(公告)日：2017-09-28

申请号：US15143160

申请日：2016-04-29

申请人： Broadcom Corporation

发明人： Dechang SUN ,  Wei ZHANG ,  Mai T. MAC LENNAN ,  Sudeep Ashok POMAR ,  Roy M. CARLSON

IPC分类号： G11C17/08

CPC分类号： G11C17/14 ,  G11C7/067 ,  G11C7/12 ,  G11C7/18 ,  G11C11/5692 ,  G11C14/00 ,  G11C17/08 ,  G11C17/10

摘要： Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.