公开(公告)号：US09553714B2

公开(公告)日：2017-01-24

申请号：US14871202

申请日：2015-09-30

Applicant: Broadcom Corporation

Inventor： Fazil Ahmad ,  Pin-En Su ,  William Huff ,  Greg Unruh

IPC: H03L7/06 ,  H04L7/00 ,  H04L7/033 ,  H03L7/099 ,  H03L7/085 ,  H03L7/18

CPC classification number: H04L7/0016 ,  H03L7/085 ,  H03L7/181 ,  H03L7/1974 ,  H04L7/0054 ,  H04L7/0331

Abstract: The problem with duty-cycle correction circuits used by conventional frequency doublers is that they typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.

Abstract translation: 常规频率倍增器使用的占空比校正电路的问题是它们通常是模拟解决方案，例如具有长链反相器或缓冲器的可变延迟线，其直接调整由锁相环（PLL）使用的参考信号。 这些解决方案可以显着增加参考信号的噪声（例如，热噪声和电源噪声），以及PLL的总功耗和成本。 本公开不是直接校正参考信号的占空比，而是涉及一种用于根据PLL产生的输出信号的周期来测量倍频参考信号的相邻周期之间的周期误差的装置和方法（ 或一些其他较高频率信号），并调整PLL分频器的分频系数以补偿测量周期误差。