公开(公告)号：US08686770B2

公开(公告)日：2014-04-01

申请号：US13962325

申请日：2013-08-08

Applicant: Broadcom Corporation

Inventor： Emmanouil Frantzeskakis ,  Georgios Sfikas ,  Stephen Wu ,  Radha Srinivasan ,  Henrik Tholstrup Jensen ,  Brima Ibrahim

IPC: H03L7/06

CPC classification number: H03L7/08 ,  H03L7/18

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract translation: 具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。 在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出 通过输入参考时钟信号和第一反馈时钟信号之间的时间差。 提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。 第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。

公开(公告)号：US20140021991A1

公开(公告)日：2014-01-23

申请号：US13962184

申请日：2013-08-08

Applicant: Broadcom Corporation

Inventor： Emmanouil Frantzeskakis ,  Georgios Sfikas ,  Stephen Wu ,  Radha Srinivasan ,  Henrik Tholstrup Jensen ,  Brima Ibrahim

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/18

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract translation: 具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。 在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出 通过输入参考时钟信号和第一反馈时钟信号之间的时间差。 提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。 第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。

公开(公告)号：US08669798B2

公开(公告)日：2014-03-11

申请号：US13962184

申请日：2013-08-08

Applicant: Broadcom Corporation

Inventor： Emmanouil Frantzeskakis ,  Georgios Sfikas ,  Stephen Wu ,  Radha Srinivasan ,  Henrik Tholstrup Jensen ,  Brima Ibrahim

IPC: H03L7/087

CPC classification number: H03L7/08 ,  H03L7/18

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract translation: 具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。 在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出 通过输入参考时钟信号和第一反馈时钟信号之间的时间差。 提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。 第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。

公开(公告)号：US20140021992A1

公开(公告)日：2014-01-23

申请号：US13962325

申请日：2013-08-08

Applicant: Broadcom Corporation

Inventor： Emmanouil Frantzeskakis ,  Georgios Sfikas ,  Stephen Wu ,  Radha Srinivasan ,  Henrik Tholstrup Jensen ,  Brima Ibrahim

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/18

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract translation: 具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。 在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出 通过输入参考时钟信号和第一反馈时钟信号之间的时间差。 提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。 第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。