公开(公告)号：US09077366B2

公开(公告)日：2015-07-07

申请号：US13969549

申请日：2013-08-17

Applicant: Broadcom Corporation

Inventor： Henrik Tholstrup Jensen ,  Jianhua Gan ,  Seema Anand ,  Aminghasem Safarian

IPC: H03M1/12 ,  H03M1/20 ,  H03M3/00

CPC classification number: H03M1/201 ,  H03M3/332 ,  H03M3/396 ,  H03M3/406 ,  H03M3/456

Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency hands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract translation: 技术和设备在两个或多个信号频率或频率手中提供模数转换，并且可用于在各种电路中构建多模式模数转换器，包括用于无线通信和无线电广播环境的接收机和收发器。 可以配置基于所述技术的可调节模数转换器，以调整电路参数，以适应不同信号频率或频段的不同输入信号的技术规格，例如无线电中的FM，HD-无线电和DAB无线电信号 接收机应用。

公开(公告)号：US20140354335A1

公开(公告)日：2014-12-04

申请号：US13966515

申请日：2013-08-14

Applicant: Broadcom Corporation

Inventor： Ioannis Loukas Syllaios ,  Henrik Tholstrup Jensen

IPC: H03L7/189

CPC classification number: H03L7/085 ,  H03L7/093 ,  H03L7/1077 ,  H03L7/16 ,  H03L7/193

Abstract: A PLL includes independent frequency-locking and phase-locking operational modes. In addition, the PLL includes a hybrid (e.g., mixed-analog/digital signal) 2nd-order delta-sigma (DS) phase/frequency detector. The detector may be implemented based on a continuous-time 1st-order DS Analog to Digital (ADC) converter. The ADC may be enhanced to 2nd-order by using, e.g., closed loop frequency detection. The PLL includes a fine resolution encoder for encoding the DS ADC output. The fine resolution encoding facilitates true multi-bit phase/frequency error digitization with drastically reduced DS quantization noise.

Abstract translation: PLL包括独立的频率锁定和相位锁定操作模式。 此外，PLL包括混合（例如，混合模拟/数字信号）二阶Δ-Σ（DS）相位/频率检测器。 检测器可以基于连续时间的一阶DS模数（ADC）转换器来实现。 可以通过使用例如闭环频率检测来将ADC增强到二阶。 PLL包括用于对DS ADC输出进行编码的精细分辨率编码器。 精细分辨率编码有助于真正的多位相位/频率误差数字化，同时显着降低DS量化噪声。

公开(公告)号：US20140021991A1

公开(公告)日：2014-01-23

申请号：US13962184

申请日：2013-08-08

Applicant: Broadcom Corporation

Inventor： Emmanouil Frantzeskakis ,  Georgios Sfikas ,  Stephen Wu ,  Radha Srinivasan ,  Henrik Tholstrup Jensen ,  Brima Ibrahim

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/18

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract translation: 具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。 在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出 通过输入参考时钟信号和第一反馈时钟信号之间的时间差。 提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。 第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。

公开(公告)号：US20130252564A1

公开(公告)日：2013-09-26

申请号：US13898287

申请日：2013-05-20

Applicant: Broadcom Corporation

Inventor： Alireza Zolfaghari ,  Henrik Tholstrup Jensen ,  Hooman Darabi

IPC: H04B1/40

CPC classification number: H04B1/406 ,  H03F3/24 ,  H04B2001/0408 ,  H04L27/0008

Abstract: Various embodiments are disclosed relating to power control techniques for wireless transmitters. In an example embodiment, an apparatus is provided that may include a digital-to-analog converter (DAC) adapted to convert a digital amplitude signal to an analog amplitude signal during a first transmission mode and adapted to convert a digital power level signal to an analog power level signal during a second transmission mode.

Abstract translation: 公开了关于无线发射机的功率控制技术的各种实施例。 在一个示例性实施例中，提供了一种可以包括数模转换器（DAC）的装置，其适于在第一传输模式期间将数字幅度信号转换为模拟幅度信号，并且适于将数字功率电平信号转换为 在第二传输模式期间的模拟功率电平信号。

公开(公告)号：US20160261024A1

公开(公告)日：2016-09-08

申请号：US14674053

申请日：2015-03-31

Applicant: Broadcom Corporation

Inventor： Henrik Tholstrup Jensen ,  Zhijiang Dong

IPC: H01Q1/24 ,  H04M1/02 ,  H04W4/00 ,  H01Q1/50

CPC classification number: H01Q1/243 ,  H01Q1/405 ,  H04M1/026 ,  H04M2250/04 ,  H04W4/80

Abstract: An antenna section includes a bracket antenna configured to send and receive RF communications of a mobile communication device having a back side that is enclosed by a back cover, wherein the bracket antenna forms a structural portion of the back cover of the mobile communication device that encloses at least one portion of an edge of the mobile communication device and at least one portion of the back side. A booster plate is coupled to the mobile communication device and is configured to electromagnetically interact with the bracket antenna to modify the antenna beam pattern.

Abstract translation: 天线部分包括配置成发送和接收具有由后盖封闭的背面的移动通信设备的RF通信的支架天线，其中所述支架天线形成所述移动通信设备的后盖的结构部分，所述后盖包围 移动通信设备的边缘的至少一部分和背侧的至少一部分。 升压板耦合到移动通信设备，并被配置为与支架天线电磁相互作用以修改天线波束图案。

公开(公告)号：US09408147B2

公开(公告)日：2016-08-02

申请号：US14023416

申请日：2013-09-10

Applicant: Broadcom Corporation

Inventor： Angel Polo ,  Farooq Muhammad Hameed ,  Hea Joung Kim ,  Ming Lin ,  Siukai Mak ,  Guoxin Xie ,  Thomas Baker ,  Prasanna Desai ,  Robert Hulvey ,  Henrik Tholstrup Jensen

IPC: H04W52/02 ,  H04W8/00 ,  H04W4/00 ,  H04B10/516 ,  H04L27/00

CPC classification number: H04W52/0229 ,  H04B10/516 ,  H04L27/0012 ,  H04W4/80 ,  H04W8/005 ,  H04W52/0216 ,  Y02D70/142 ,  Y02D70/144

Abstract: A method of communicating data in a Bluetooth™ low energy (BLE) module is provided. The method includes modulating an outbound communication signal into a modulated signal with a particular modulation scheme based on a modulation type, and transmitting the modulated signal to a remote device via a wireless communication connection associated with the modulation type. The method also includes receiving an inbound radio frequency (RF) signal, determining if the inbound RF signal is associated with a modulation type, and demodulating the inbound RF signal with a particular modulation scheme based on the modulation type if the inbound RF signal is determined to be associated with a modulation type. In some aspects, the inbound RF signal and outbound modulated signal have symbol rates of 2 Megasymbols per second. In some implementations, the method includes switching between a legacy BLE system and an enhanced rate BLE system.

Abstract translation: 提供了一种在Bluetooth™低能量（BLE）模块中传送数据的方法。 该方法包括：基于调制类型，将出站通信信号调制成具有特定调制方式的调制信号，并通过与调制类型相关联的无线通信连接将调制信号发送到远程设备。 该方法还包括接收入站射频（RF）信号，确定入站RF信号是否与调制类型相关联，并且如果确定了入站RF信号，则基于调制类型来解调具有特定调制方案的入站RF信号 与调制类型相关联。 在一些方面，入站RF信号和出站调制信号的符号速率为每秒2兆符号。 在一些实现中，该方法包括在传统BLE系统和增强速率BLE系统之间进行切换。

公开(公告)号：US08669798B2

公开(公告)日：2014-03-11

申请号：US13962184

申请日：2013-08-08

Applicant: Broadcom Corporation

Inventor： Emmanouil Frantzeskakis ,  Georgios Sfikas ,  Stephen Wu ,  Radha Srinivasan ,  Henrik Tholstrup Jensen ,  Brima Ibrahim

IPC: H03L7/087

CPC classification number: H03L7/08 ,  H03L7/18

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract translation: 具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。 在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出 通过输入参考时钟信号和第一反馈时钟信号之间的时间差。 提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。 第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。

公开(公告)号：US09319051B2

公开(公告)日：2016-04-19

申请号：US14283652

申请日：2014-05-21

Applicant: Broadcom Corporation

Inventor： Ioannis Loukas Syllaios ,  Henrik Tholstrup Jensen

IPC: H03L7/093 ,  H03L7/107 ,  H03L7/193

CPC classification number: H03L7/093 ,  H03L7/1075 ,  H03L7/193

Abstract: Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (ΔΣ) phase/frequency detector (ΔΣ PFD). A hybrid 2nd-order ΔΣ PFD may be implemented based on a continuous-time 1st-order ΔΣ analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the ΔΣ PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced ΔΣ quantization noise. The implementation of low complexity ΔΣ PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO).

Abstract translation: 具有动态混合（混合模拟/数字信号）Δ-Σ（＆Dgr＆amp;＆Sgr）相位/频率检测器（＆Dgr＆amp; PFG）的数字锁相环（PLL）。 混合二级＆Dgr＆ PFD可以基于连续时间的一阶＆Dgr＆amp; 模数转换器（ADC）通过闭环频率检测增强到二阶。 ＆Dgr＆Sgr的精细分辨率编码 PFD输出可以实现真正的多位相位/频率误差数字化，显着降低了Dgr＆ 量化噪声。 低复杂度的实现＆Dgr＆ 通过数字重新量化和自适应噪声消除来辅助PFD。 PLL包括独立的频率锁定和相位锁定操作模式以及数字控制振荡器（DCO）的全数字控制。

公开(公告)号：US20150118956A1

公开(公告)日：2015-04-30

申请号：US14062389

申请日：2013-10-24

Applicant: Broadcom Corporation

Inventor： Prasanna Desai ,  John Walley ,  Henrik Tholstrup Jensen ,  Steven Deane Hall ,  Domitille Esnard-Domerego ,  Hea Joung Kim ,  Yasantha Rajakarunanayake ,  Ming Lin ,  Vadim Bishtein ,  Nhan Quang Tran ,  Ntsanderh Azenui

IPC: H04B5/00

CPC classification number: H04B5/0037 ,  H04B5/0031 ,  H04B5/0075

Abstract: A communication device includes a first and second near-field wireless (NFW) module operating with a first and second protocol, respectively. A module and method to improve the operational efficiency of the first and second NFW modules are disclosed. Due to close proximity between the first and second NFW modules in the communication device, an undesirable parasitic inductive coupling can occur that can degrade the operational performance of the modules. The first NFW module can be configured to control inductive coupling of the second NFW module when an electromagnetic (EM) field operating with the first protocol is detected. Additionally, the second NFW module can be configured to control inductive coupling of the first NFW module when an EM field operating with the second protocol is detected. Controlling the inductive coupling of each module can be performed by means of detuning an inductive coupling element of each module.

Abstract translation: 通信设备包括分别以第一和第二协议操作的第一和第二近场无线（NFW）模块。 公开了一种用于提高第一和第二NFW模块的操作效率的模块和方法。 由于通信设备中第一和第二NFW模块之间的紧密接近，可能会发生不利的寄生电感耦合，这可能降低模块的操作性能。 当检测到用第一协议操作的电磁（EM）场时，第一NFW模块可被配置为控制第二NFW模块的电感耦合。 另外，当检测到用第二协议操作的EM场时，第二NFW模块可被配置为控制第一NFW模块的电感耦合。 控制每个模块的电感耦合可以通过使每个模块的电感耦合元件失谐来实现。

公开(公告)号：US20140354336A1

公开(公告)日：2014-12-04

申请号：US14283652

申请日：2014-05-21

Applicant: Broadcom Corporation

Inventor： Ioannis Loukas Syllaios ,  Henrik Tholstrup Jensen

IPC: H03L7/189

CPC classification number: H03L7/093 ,  H03L7/1075 ,  H03L7/193

Abstract: Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (ΔΣ) phase/frequency detector (ΔΣ PFD). A hybrid 2nd-order ΔΣ PFD may be implemented based on a continuous-time 1st-order ΔΣ analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the ΔΣ PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced ΔΣ quantization noise. The implementation of low complexity ΔΣ PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO).

Abstract translation: 具有动态混合（混合模拟/数字信号）Δ-Σ（＆Dgr＆amp;＆Sgr）相位/频率检测器（＆Dgr＆amp; PFG）的数字锁相环（PLL）。 混合二级＆Dgr＆ PFD可以基于连续时间的一阶＆Dgr＆amp; 模数转换器（ADC）通过闭环频率检测增强到二阶。 ＆Dgr＆Sgr的精细分辨率编码 PFD输出可以实现真正的多位相位/频率误差数字化，显着降低了Dgr＆ 量化噪声。 低复杂度的实现＆Dgr＆ 通过数字重新量化和自适应噪声消除来辅助PFD。 PLL包括独立的频率锁定和相位锁定操作模式以及数字控制振荡器（DCO）的全数字控制。