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11 条记录 (耗时 0.184 秒)

    Closed loop power normalized timing recovery for 8 VSB modulated signals
    1.
    发明授权
    Closed loop power normalized timing recovery for 8 VSB modulated signals 有权
    8路VSB调制信号的闭环功率归一化定时恢复

    公开(公告)号：US08315345B2

    公开(公告)日：2012-11-20

    申请号：US12916977

    申请日：2010-11-01

    申请人： Bruno Amizic ,  Tyler Brown

    发明人： Bruno Amizic ,  Tyler Brown

    IPC分类号： H04L7/00

    CPC分类号： H04L27/06 ,  H04L7/007 ,  H04L7/0278

    摘要： A timing recovery loop includes a sampler, a narrow band filter, an RMS normalize, a timing error detector, and a sample controller. The sampler samples a received signal. The narrow band filter filters the sampled received signal so as to pass an upper band edge of the received signal and not a lower band edge of the received signal. The RMS normalize sets an average power level of an output of the filter to a substantially constant value. The timing error detector detects a timing error with respect to an output of the RMS normalize. The sample controller controls the sampler in response to the detected timing error.

    摘要翻译： 定时恢复回路包括采样器，窄带滤波器，RMS归一化，定时误差检测器和采样控制器。 采样器对接收到的信号进行采样。 窄带滤波器对采样的接收信号进行滤波，以便通过接收信号的较高频带边沿，而不是接收信号的较低频带边沿。 RMS归一化将滤波器的输出的平均功率电平设置为基本上恒定的值。 定时误差检测器检测相对于RMS归一化的输出的定时误差。 样品控制器响应于检测到的定时误差控制采样器。

    Closed loop power normalized timing recovery for 8 VSB modulated signals
    6.
    发明授权
    Closed loop power normalized timing recovery for 8 VSB modulated signals 有权
    8路VSB调制信号的闭环功率归一化定时恢复

    公开(公告)号：US08189724B1

    公开(公告)日：2012-05-29

    申请号：US11258700

    申请日：2005-10-26

    申请人： Bruno Amizic ,  Tyler Brown

    发明人： Bruno Amizic ,  Tyler Brown

    IPC分类号： H04L7/00

    CPC分类号： H04L27/06 ,  H04L7/007 ,  H04L7/0278

    摘要： A timing recovery loop includes a sampler, a narrow band filter, an RMS normalizer, a timing error detector, and a sample controller. The sampler samples a received signal. The narrow band filter filters the sampled received signal so as to pass an upper band edge of the received signal and not a lower band edge of the received signal. The RMS normalizer sets an average power level of an output of the filter to a substantially constant value. The timing error detector detects a timing error with respect to an output of the RMS normalizer. The sample controller controls the sampler in response to the detected timing error.

    摘要翻译： 定时恢复循环包括采样器，窄带滤波器，RMS归一化器，定时误差检测器和样本控制器。 采样器对接收到的信号进行采样。 窄带滤波器对采样的接收信号进行滤波，以便通过接收信号的较高频带边沿，而不是接收信号的较低频带边沿。 RMS均衡器将滤波器的输出的平均功率电平设置为基本上恒定的值。 定时误差检测器检测相对于RMS归一化器的输出的定时误差。 样品控制器响应于检测到的定时误差控制采样器。

    CLOSED LOOP POWER NORMALIZED TIMING RECOVERY FOR 8 VSB MODULATED SIGNALS
    7.
    发明申请
    CLOSED LOOP POWER NORMALIZED TIMING RECOVERY FOR 8 VSB MODULATED SIGNALS 有权
    关闭8V VSB调制信号的闭环正常定时恢复

    公开(公告)号：US20110044381A1

    公开(公告)日：2011-02-24

    申请号：US12916977

    申请日：2010-11-01

    申请人： Bruno Amizic ,  Tyler Brown

    发明人： Bruno Amizic ,  Tyler Brown

    IPC分类号： H04L27/08 ,  H04B17/00

    CPC分类号： H04L27/06 ,  H04L7/007 ,  H04L7/0278

    摘要： A timing recovery loop includes a sampler, a narrow band filter, an RMS normalizer, a timing error detector, and a sample controller. The sampler samples a received signal. The narrow band filter filters the sampled received signal so as to pass an upper band edge of the received signal and not a lower band edge of the received signal. The RMS normalizer sets an average power level of an output of the filter to a substantially constant value. The timing error detector detects a timing error with respect to an output of the RMS normalizer. The sample controller controls the sampler in response to the detected timing error.

    摘要翻译： 定时恢复循环包括采样器，窄带滤波器，RMS归一化器，定时误差检测器和样本控制器。 采样器对接收到的信号进行采样。 窄带滤波器对采样的接收信号进行滤波，以便通过接收信号的较高频带边沿，而不是接收信号的较低频带边沿。 RMS均衡器将滤波器的输出的平均功率电平设置为基本上恒定的值。 定时误差检测器检测相对于RMS归一化器的输出的定时误差。 样品控制器响应于检测到的定时误差控制采样器。

    Channel impulse response estimating decision feedback equalizer
    8.
    发明申请
    Channel impulse response estimating decision feedback equalizer 有权
    信道脉冲响应估计判决反馈均衡器

    公开(公告)号：US20050254570A1

    公开(公告)日：2005-11-17

    申请号：US10911282

    申请日：2004-08-04

    申请人： Bruno Amizic ,  Mark Fimoff ,  Jin Kim ,  Sreenivasa Nerayanuru

    发明人： Bruno Amizic ,  Mark Fimoff ,  Jin Kim ,  Sreenivasa Nerayanuru

    IPC分类号： H04L1/00 ,  H04L25/03 ,  H04L5/12

    CPC分类号： H04L25/03057 ,  H04L2025/03382 ,  H04L2025/0349

    摘要： A decision feedback equalizer is operated by making first symbol decisions from an output of the decision feedback equalizer such that the first symbol decisions are characterized by a relatively long processing delay, by making second symbol decisions from the output of the decision feedback equalizer such that the second symbol decisions are characterized by a relatively short processing delay, and by determining tap weights for the decision feedback equalizer based on the first and second symbol decisions. The first symbol decisions may be derived from the output of a long traceback trellis decoder. The second symbol decisions may be derived either from the output of a short traceback trellis decoder or from shorter delay outputs of the long traceback trellis decoder.

    摘要翻译： 通过从所述判决反馈均衡器的输出进行第一符号判定来操作判定反馈均衡器，以便通过从所述判决反馈均衡器的输出进行第二符号判定，使得所述第一符号判定由相对长的处理延迟表征，使得 第二符号决定的特征在于相对短的处理延迟，并且通过基于第一和第二符号决定确定用于判决反馈均衡器的抽头权重。 第一符号决定可以从长跟踪网格解码器的输出中导出。 第二符号决定可以从短跟踪网格解码器的输出或长跟踪网格解码器的较短延迟输出中导出。

    Channel impulse response estimating decision feedback equalizer
    9.
    发明授权
    Channel impulse response estimating decision feedback equalizer 有权
    信道脉冲响应估计判决反馈均衡器

    公开(公告)号：US08320442B2

    公开(公告)日：2012-11-27

    申请号：US10911282

    申请日：2004-08-04

    申请人： Bruno Amizic ,  Mark Fimoff ,  Jin Kim ,  Sreenivasa M. Nerayanuru

    发明人： Bruno Amizic ,  Mark Fimoff ,  Jin Kim ,  Sreenivasa M. Nerayanuru

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03057 ,  H04L2025/03382 ,  H04L2025/0349

    摘要： A decision feedback equalizer is operated by making first symbol decisions from an output of the decision feedback equalizer such that the first symbol decisions are characterized by a relatively long processing delay, by making second symbol decisions from the output of the decision feedback equalizer such that the second symbol decisions are characterized by a relatively short processing delay, and by determining tap weights for the decision feedback equalizer based on the first and second symbol decisions. The first symbol decisions may be derived from the output of a long traceback trellis decoder. The second symbol decisions may be derived either from the output of a short traceback trellis decoder or from shorter delay outputs of the long traceback trellis decoder.

    摘要翻译： 通过从所述判决反馈均衡器的输出进行第一符号判定来操作判定反馈均衡器，以便通过从所述判决反馈均衡器的输出进行第二符号判定，使得所述第一符号判定由相对长的处理延迟表征，使得 第二符号决定的特征在于相对短的处理延迟，并且通过基于第一和第二符号决定确定用于判决反馈均衡器的抽头权重。 第一符号决定可以从长跟踪网格解码器的输出中导出。 第二符号决定可以从短跟踪网格解码器的输出或长跟踪网格解码器的较短延迟输出中导出。

    Cir estimating decision feedback equalizer with phase tracker
    10.
    发明申请
    Cir estimating decision feedback equalizer with phase tracker 有权
    Cir使用相位跟踪器估计判决反馈均衡器

    公开(公告)号：US20060239342A1

    公开(公告)日：2006-10-26

    申请号：US11114573

    申请日：2005-04-26

    申请人： Bruno Amizic ,  Mark Fimoff ,  Sreenivasa Nerayanuru

    发明人： Bruno Amizic ,  Mark Fimoff ,  Sreenivasa Nerayanuru

    IPC分类号： H03H7/40 ,  H03K5/159

    CPC分类号： H04L25/0212 ,  H04L25/03057 ,  H04L25/03203

    摘要： An equalizer system includes an equalizer, first and second decoders, and a tap weight controller. The equalizer equalizes a received signal to provide an equalizer output. The first decoder is characterized by a first parallel output, and the first decoder decodes the equalizer output to provide first symbol decisions having a first accuracy. The second decoder is characterized by a second parallel output, the second decoder receives the first parallel output and decodes the equalizer output to provide second symbol decisions having a second accuracy, the first accuracy is greater than the second accuracy, and the second decoder applies the second parallel output to the equalizer. The tap weight controller determines tap weights based on the first symbol decisions and supplies the tap weights to the equalizer.

    摘要翻译： 均衡器系统包括均衡器，第一和第二解码器以及抽头加权控制器。 均衡器对接收到的信号进行均衡以提供均衡器输出。 第一解码器的特征在于第一并行输出，并且第一解码器解码均衡器输出以提供具有第一精度的第一符号决定。 第二解码器的特征在于第二并行输出，第二解码器接收第一并行输出并解码均衡器输出以提供具有第二精度的第二符号决定，第一精度大于第二精度，第二解码器应用 第二并行输出到均衡器。 抽头重量控制器基于第一符号决定确定抽头权重，并将抽头权重提供给均衡器。