利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

156 条记录 (耗时 0.02 秒)

    Simultaneous transmission of clock and bidirectional data over a communication channel
    5.
    发明授权
    Simultaneous transmission of clock and bidirectional data over a communication channel 有权
    通过通信通道同时传输时钟和双向数据

    公开(公告)号：US08958497B2

    公开(公告)日：2015-02-17

    申请号：US13834927

    申请日：2013-03-15

    申请人： Silicon Image, Inc.

    发明人： Inyeol Lee ,  Baegin Sung ,  Hanwoong Sohn ,  Shinje Tahk ,  Sun Woo Baek ,  Chandlee B. Harrell

    IPC分类号： H04B15/00 ,  H04B7/015 ,  H04L25/49 ,  H04B3/23

    CPC分类号： H04L7/0087 ,  H04B3/23 ,  H04B7/015 ,  H04L7/0278 ,  H04L7/033 ,  H04L7/042 ,  H04L25/4904 ,  H04L25/493

    摘要： Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.

    摘要翻译： 本发明的实施例一般涉及通过通信信道同时传输时钟和双向数据。 发射装置的实施例包括调制器，用于产生包括时钟信号和数据信号的调制信号，时钟信号由调制信号的第一信号边沿调制，数据信号由第二信号的位置调制 调制信号的边缘; 在通信信道上驱动调制信号的驱动器; 回波消除器，用于减去通信信道上的反射信号; 以及数据恢复模块，用于恢复在通信信道上接收到的信号，所述接收信号通过归零（RZ）编码进行编码，该信号与在通信信道上驱动调制信号同时接收。

    Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets
    6.
    发明申请
    Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets 有权
    用于管理频率偏移系统中的多个时钟域的相位控制块

    公开(公告)号：US20150030113A1

    公开(公告)日：2015-01-29

    申请号：US14321723

    申请日：2014-07-01

    申请人： Rambus Inc.

    发明人： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

    IPC分类号： H04L7/033 ,  H04L7/00

    CPC分类号： H04L7/0278 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337 ,  H04L7/0338

    摘要： A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

    摘要翻译： 用于根据接收到的数字信号30执行时钟恢复的电路。该电路至少包括用于对数字信号进行采样的边缘采样器105和数据采样器145以及时钟信号提供电路。 时钟信号供应电路提供边缘时钟25和数据时钟20信号，其相位偏移到边缘采样器105和数据采样器145的相应时钟输入。时钟信号供应电路可操作以选择性地改变相位偏移 边沿和数据时钟信号。

    Timing recovery apparatus and method
    7.
    发明授权
    Timing recovery apparatus and method 有权
    定时回收装置及方法

    公开(公告)号：US08942328B2

    公开(公告)日：2015-01-27

    申请号：US14132372

    申请日：2013-12-18

    申请人： MStar Semiconductor, Inc.

    发明人： Ko-Yin Lai ,  Chun-Chi Su ,  Chih-Cheng Kuo ,  Chia-Sheng Peng

    IPC分类号： H04L27/08 ,  H04L7/00 ,  H04L1/00 ,  H04L7/027

    CPC分类号： H04L7/0016 ,  H04L1/0036 ,  H04L7/0278

    摘要： A timing recovery apparatus for compensating a sampling frequency offset of an input signal is provided. The timing recovery apparatus includes a timing error corrector configured to generate an output signal according to the input signal and a calibration signal, a gain controller configured to adjust at least one of a signal edge low-frequency error component and a signal edge high-frequency error component of the output signal and accordingly generate an adjusted signal, a timing error detector configured to generate an error signal according to the adjusted signal, and a calibration signal generator coupled to the timing error detector and the timing error corrector, for generating the calibration signal according to the error signal and outputting the calibration signal to the timing error corrector to compensate the sampling frequency offset of the input signal.

    摘要翻译： 提供了用于补偿输入信号的采样频率偏移的定时恢复装置。 定时恢复装置包括定时误差校正器，其被配置为根据输入信号和校准信号生成输出信号;增益控制器，被配置为调整信号边缘低频误差分量和信号边缘高频中的至少一个 输出信号的误差分量，并因此产生经调整的信号;定时误差检测器，被配置为根据调整后的信号产生误差信号;以及校准信号发生器，耦合到定时误差检测器和定时误差校正器，用于产生校准 信号，并将校准信号输出到定时误差校正器，以补偿输入信号的采样频率偏移。

    Universal timing recovery circuit
    8.
    发明授权
    Universal timing recovery circuit 有权
    通用定时恢复电路

    公开(公告)号：US08488697B2

    公开(公告)日：2013-07-16

    申请号：US13102530

    申请日：2011-05-06

    申请人： Michael Paul Fitz ,  Scott Warren Enserink ,  Isaak John Woldeit

    发明人： Michael Paul Fitz ,  Scott Warren Enserink ,  Isaak John Woldeit

    IPC分类号： H04K1/10

    CPC分类号： H04L7/0278

    摘要： A timing recovery system that provides a timing estimate between a transmitter clock and a receiver clock. The system includes a down-converter that converts a received intermediate frequency signal in the receiver and down-converts, using Fs/4 down-conversion, the received signal into baseband in-phase and quadrature phase signals. The baseband in-phase and quadrature phase signals are sent to a direct down-converter that frequency shifts the in-phase and quadrature phase. The frequency-shifted in-phase and quadrature phase baseband signals are then low-pass filtered in order to isolate the frequency components of interest, reduce noise, and remove zeros that are artifacts of the Fs/4 down-conversion. The signals are sent to a square-law non-linearity circuit that provides squaring non-linearity to generate non-linear in-phase and quadrature phase signals. The non-linear in-phase and quadrature phase signals are sent to a single-pole, low-pass post-filter circuit that generates the timing estimate.

    摘要翻译： 定时恢复系统，其提供发射机时钟和接收机时钟之间的定时估计。 该系统包括一个下变频器，其转换接收机中接收到的中频信号，并使用Fs / 4下变频将接收的信号下变频为基带同相和正交相位信号。 基带同相和正交相位信号被发送到频率偏移同相和正交相位的直接下变频器。 然后对频移的同相和正交相位基带信号进行低通滤波，以隔离感兴趣的频率分量，降低噪声，并除去作为Fs / 4下转换的伪影的零点。 信号被发送到平方律非线性电路，其提供平方非线性以产生非线性同相和正交相位信号。 非线性同相和正交相位信号被发送到产生定时估计的单极，低通后置滤波器电路。

    Closed loop power normalized timing recovery for 8 VSB modulated signals
    9.
    发明授权
    Closed loop power normalized timing recovery for 8 VSB modulated signals 有权
    8路VSB调制信号的闭环功率归一化定时恢复

    公开(公告)号：US08189724B1

    公开(公告)日：2012-05-29

    申请号：US11258700

    申请日：2005-10-26

    申请人： Bruno Amizic ,  Tyler Brown

    发明人： Bruno Amizic ,  Tyler Brown

    IPC分类号： H04L7/00

    CPC分类号： H04L27/06 ,  H04L7/007 ,  H04L7/0278

    摘要： A timing recovery loop includes a sampler, a narrow band filter, an RMS normalizer, a timing error detector, and a sample controller. The sampler samples a received signal. The narrow band filter filters the sampled received signal so as to pass an upper band edge of the received signal and not a lower band edge of the received signal. The RMS normalizer sets an average power level of an output of the filter to a substantially constant value. The timing error detector detects a timing error with respect to an output of the RMS normalizer. The sample controller controls the sampler in response to the detected timing error.

    摘要翻译： 定时恢复循环包括采样器，窄带滤波器，RMS归一化器，定时误差检测器和样本控制器。 采样器对接收到的信号进行采样。 窄带滤波器对采样的接收信号进行滤波，以便通过接收信号的较高频带边沿，而不是接收信号的较低频带边沿。 RMS均衡器将滤波器的输出的平均功率电平设置为基本上恒定的值。 定时误差检测器检测相对于RMS归一化器的输出的定时误差。 样品控制器响应于检测到的定时误差控制采样器。