公开(公告)号：US5679609A

公开(公告)日：1997-10-21

申请号：US631756

申请日：1996-04-12

申请人： Bruno Roberto Aimi ,  John Edward Cronin ,  Andre Conrad Forcier ,  James Marc Leas ,  Patricia McGuinnes Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： Bruno Roberto Aimi ,  John Edward Cronin ,  Andre Conrad Forcier ,  James Marc Leas ,  Patricia McGuinnes Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L21/82 ,  G01R31/28 ,  H01L21/66 ,  H01L23/52 ,  H01L25/065 ,  H01L21/60

CPC分类号： G01R31/2863 ,  G01R31/2884 ,  H01L22/22 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002

摘要： A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity. The second conductive level includes islands of strap conductors that electrically interconnect the isolated conductors of the first conductive level. The first conductive level and a second conductive level are constructed of different conductive material which may be separately etched so that the second conductive level may be removed without affecting this first conductive level.

公开(公告)号：US5661330A

公开(公告)日：1997-08-26

申请号：US404005

申请日：1995-03-14

申请人： Bruno Roberto Aimi ,  John Edward Cronin ,  Andre Conrad Forcier ,  James Marc Leas ,  Patricia McGuinnes Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： Bruno Roberto Aimi ,  John Edward Cronin ,  Andre Conrad Forcier ,  James Marc Leas ,  Patricia McGuinnes Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L21/82 ,  G01R31/28 ,  H01L21/66 ,  H01L23/52 ,  H01L25/065 ,  H01L29/00

CPC分类号： G01R31/2863 ,  G01R31/2884 ,  H01L22/22 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002

摘要： A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity. The second conductive level includes islands of strap conductors that electrically interconnect the isolated conductors of the first conductive level. The first conductive level and a second conductive level are constructed of different conductive material which may be separately etched so that the second conductive level may be removed without affecting this first conductive level.

摘要翻译： 本发明提供一种具有连接组件的多芯片半导体结构和制造方法，其具有促进烧结应力和结构电气测试的熔断器。 该结构包括具有到其边缘表面的标准传输线的多芯片叠层。 至少一些到边缘表面的导线具有电连接到其上的熔丝，使得在老化应力期间应当产生过大的电流源/漏，相应的保险丝将断开。 还公开了导电结构，其有助于在老化应力和测试之前在多芯片结构的边缘表面上形成最终的可操作的金属化布线。 该导电结构包括第一导电水平和第二导电水平。 第一导电电平具有绝缘导体，其端部紧邻设置。 第二导电电平包括带状导体岛，其电连接第一导电电平的隔离导体。 第一导电水平和第二导电水平由不同的导电材料构成，其可以被单独蚀刻，使得可以去除第二导电水平而不影响该第一导电水平。