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公开(公告)号：US6037786A
公开(公告)日：2000-03-14
申请号：US767999
申请日：1996-12-13
CPC分类号： G01R1/0466 , H01L2224/0401 , H01L2224/05557 , H01L2224/81191 , H01L2224/81385 , Y10T29/49155
摘要： An interposer for making a penetrating temporary contact between the contact pads of a chip having bumped or unbumped I/O pads and a test board for the purpose of testing the chip is disclosed. The interposer comprises a silicon substrate having sharp penetrating structures integrally formed at a predetermined depth in the silicon substrate along crystallographic planes. The resultant apparatus has a matching lateral thermal expansion to the chip being tested and provides uniform contact to all chip I/O pads.
摘要翻译： 公开了一种用于在具有凸起或未凸起的I / O焊盘的芯片的接触焊盘之间进行穿透性临时接触的插入件和用于测试芯片的测试板。 插入器包括具有沿着晶面平行于硅衬底中的预定深度一体形成的尖锐穿透结构的硅衬底。 所得到的装置具有与所测试的芯片的匹配横向热膨胀，并提供与所有芯片I / O焊盘的均匀接触。
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2.发明授权Method for forming an interposer for making temporary contact with pads of a semiconductor chip 失效用于形成用于与半导体芯片的焊盘暂时接触的插入件的方法公开(公告)号：US06188231B1
公开(公告)日：2001-02-13
申请号：US09453130
申请日：1999-12-02
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , H01L2224/0401 , H01L2224/05557 , H01L2224/81191 , H01L2224/81385 , Y10T29/49155
摘要： An interposer for making a penetrating temporary contact between the contact pads of a chip having bumped or unbumped I/O pads and a test board for the purpose of testing said chip is disclosed. The interposer comprises a silicon substrate having sharp penetrating structures integrally formed at a predetermined depth in the silicon substrate along crystallographic planes. The resultant apparatus has a matching lateral thermal expansion to the chip being tested and provides uniform contact to all chip I/O pads.
摘要翻译： 公开了一种用于在具有凸起或未凸起的I / O焊盘的芯片的接触焊盘之间进行穿透性临时接触的插入件和用于测试所述芯片的测试板。 插入器包括具有沿着晶面平行于硅衬底中的预定深度一体形成的尖锐穿透结构的硅衬底。 所得到的装置具有与所测试的芯片的匹配横向热膨胀，并提供与所有芯片I / O焊盘的均匀接触。
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公开(公告)号：US6059982A
公开(公告)日：2000-05-09
申请号：US940916
申请日：1997-09-30
CPC分类号： G01R3/00 , B82Y35/00 , G01R1/06761 , Y10T29/42 , Y10T29/49117 , Y10T29/49155
摘要： A probe assembly including an integral fine probe tip, conductive line with terminal connection for testing semiconductor devices and a method of construction of the probe assembly is described. The method of construction described utilizes the step of etching pits into silicon wafers to produce molds for forming the probe point. Semiconductor machining processes are used to complete the probe assembly.
摘要翻译： 描述了一种探针组件，其包括整体精细探针尖端，具有用于测试半导体器件的端子连接的导线以及探针组件的构造方法。 所描述的结构的方法利用将凹坑蚀刻成硅晶片以产生用于形成探针点的模具的步骤。 半导体加工工艺用于完成探针组件。
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公开(公告)号：US6014032A
公开(公告)日：2000-01-11
申请号：US940915
申请日：1997-09-30
CPC分类号： G01R1/06711 , G01R1/07342
摘要： A multi-probe ring assembly including integral fine probe tips, conductive lines with terminal connection for testing semiconductor devices and a method of construction of the multi-probe ring assembly is described. The method of construction described utilizes the step of etching pits into silicon wafers to produce molds for forming the probe points. Semiconductor machining processes are used to complete the probe ring assembly.
摘要翻译： 描述了包括整体精细探针尖端，具有用于测试半导体器件的端子连接的导线以及多探针环组件的构造方法的多探针环组件。 所描述的结构的方法利用将凹坑蚀刻到硅晶片中以形成用于形成探针点的模具的步骤。 半导体加工工艺用于完成探头环组件。
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公开(公告)号：US5751057A
公开(公告)日：1998-05-12
申请号：US728534
申请日：1996-10-09
IPC分类号： H01L23/50 , H01L23/495 , H01L23/52
CPC分类号： H01L23/4951 , H01L2224/32245 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/14
摘要： Lead On Chip ("LOC") leadframe designs for thin, small-outline packages having improved configurations of leadframe members are provided. The LOC leadframes comprise a bus bar, having at least one distribution finger, and a plurality of lead fingers arranged in such a manner that jump-over is eliminated, thus increasing the reliability of the package.
摘要翻译： 提供了具有改进的引线框架构件配置的薄型小外形封装的引线框设计（“LOC”）引线框设计。 LOC引线框架包括具有至少一个分配指状物的汇流条和以这样的方式排列的多个引线，从而提高了封装的可靠性。
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公开(公告)号：US5874782A
公开(公告)日：1999-02-23
申请号：US518740
申请日：1995-08-24
CPC分类号： H01L24/10 , H01L21/563 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2224/73203 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： Disclosed is a semiconductor wafer, and the method of making the same, the wafer being formed to have a multiplicity of raised contact pads on its surface. The contact pads are formed with conductors which are disposed on the surface of the wafer and which are coupled to internal circuitry embedded in the wafer through vias in the wafer's surface. The contact pads are in a raised elevational relationship relative to the surface conductors. After the wafer is fully processed, by dicing individual integrated circuit chips out of the wafer, each chip can then be mounted on a higher level of assembly, such as a printed circuit board. The raised contact pads originally formed on the wafer, and therefore formed on each individual chip, provide the contact points by which the chip can be bonded with matingly arranged contact pads on the higher level of assembly.
摘要翻译： 公开了一种半导体晶片及其制造方法，晶片形成为在其表面上具有多个凸起的接触焊盘。 接触焊盘由导体组成，它们设置在晶片的表面上，并通过晶片表面中的通孔与嵌入晶片的内部电路相连。 接触垫相对于表面导体处于升高的高度关系。 在晶片完全处理之后，通过将单个集成电路芯片切割出晶片，每个芯片然后可以安装在诸如印刷电路板的更高级别的组件上。 原来形成在晶片上并因此形成在每个单独芯片上的凸起接触垫提供接触点，通过该接触点，芯片可以在更高级别的组件上配合布置的接触焊盘接合。
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7.发明授权Fabrication, testing and repair of multichip semiconductor structures having connect assemblies with fuses 失效具有熔断器连接组件的多芯片半导体结构的制造，测试和修复
公开(公告)号：US5661330A
公开(公告)日：1997-08-26
申请号：US404005
申请日：1995-03-14
申请人： Bruno Roberto Aimi , John Edward Cronin , Andre Conrad Forcier , James Marc Leas , Patricia McGuinnes Marmillion , Anthony Michael Palagonia , Bernadette Ann Pierson , Dennis Arthur Schmidt
发明人： Bruno Roberto Aimi , John Edward Cronin , Andre Conrad Forcier , James Marc Leas , Patricia McGuinnes Marmillion , Anthony Michael Palagonia , Bernadette Ann Pierson , Dennis Arthur Schmidt
CPC分类号： G01R31/2863 , G01R31/2884 , H01L22/22 , H01L25/0657 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2924/0002
摘要： A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity. The second conductive level includes islands of strap conductors that electrically interconnect the isolated conductors of the first conductive level. The first conductive level and a second conductive level are constructed of different conductive material which may be separately etched so that the second conductive level may be removed without affecting this first conductive level.
摘要翻译： 本发明提供一种具有连接组件的多芯片半导体结构和制造方法，其具有促进烧结应力和结构电气测试的熔断器。 该结构包括具有到其边缘表面的标准传输线的多芯片叠层。 至少一些到边缘表面的导线具有电连接到其上的熔丝，使得在老化应力期间应当产生过大的电流源/漏，相应的保险丝将断开。 还公开了导电结构，其有助于在老化应力和测试之前在多芯片结构的边缘表面上形成最终的可操作的金属化布线。 该导电结构包括第一导电水平和第二导电水平。 第一导电电平具有绝缘导体，其端部紧邻设置。 第二导电电平包括带状导体岛，其电连接第一导电电平的隔离导体。 第一导电水平和第二导电水平由不同的导电材料构成，其可以被单独蚀刻，使得可以去除第二导电水平而不影响该第一导电水平。
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公开(公告)号：US06239469B1
公开(公告)日：2001-05-29
申请号：US09677059
申请日：2000-09-29
IPC分类号： H01L2701
CPC分类号： H01L21/76264 , H01L21/76272 , H01L21/76283
摘要： A method for forming a silicon on insulator region on a single crystal silicon substrate, comprising the steps of: forming a first dielectric region in a silicon substrate by etching, deposition, and chemical-mechanical polishing; forming a single crystal layer on the substrate by polysilicon deposition and re-growth or epitaxial growth; removing portions of the single crystal layer to produce silicon islands that are fully on the first dielectric region; and filling in the spaces between the silicon islands with a second dielectric, by deposition and chemical-mechanical-polish, that overlaps peripheral portions of the first dielectric. Additional steps subdivide the fully isolated silicon on insulator regions by etching trenches in the islands and backfilling with a third dielectric, by deposition and chemical-mechanical-polish.
摘要翻译： 一种在单晶硅衬底上形成绝缘体上硅区域的方法，包括以下步骤：通过蚀刻，沉积和化学机械抛光在硅衬底中形成第一电介质区域; 通过多晶硅沉积和再生长或外延生长在衬底上形成单晶层; 去除单晶层的部分以产生完全在第一介电区域上的硅岛; 以及通过与第一电介质的外围部分重叠的沉积和化学机械抛光来填充硅岛之间的空间与第二电介质。 附加步骤通过蚀刻岛中的沟槽并通过沉积和化学机械抛光来用第三电介质回填来细分绝缘体上的完全隔离的区域。
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公开(公告)号：US06232143B1
公开(公告)日：2001-05-15
申请号：US09448110
申请日：1999-11-23
IPC分类号： H01L2144
CPC分类号： G01R1/06711 , G01R1/07342
摘要： A multi-probe ring assembly including integral fine probe tips, conductive lines with terminal connection for testing semiconductor devices and a method of construction of the multi-probe ring assembly is described. The method of construction described utilizes the step of etching pits into silicon wafers to produce molds for forming the probe points. Semiconductor machining processes are used to complete the probe ring assembly.
摘要翻译： 描述了包括整体精细探针尖端，具有用于测试半导体器件的端子连接的导线以及多探针环组件的构造方法的多探针环组件。 所描述的结构的方法利用将凹坑蚀刻到硅晶片中以形成用于形成探针点的模具的步骤。 半导体加工工艺用于完成探头环组件。
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公开(公告)号：US5907785A
公开(公告)日：1999-05-25
申请号：US826362
申请日：1997-03-26
IPC分类号： H01L21/56 , H01L23/485 , H01L21/44
CPC分类号： H01L24/10 , H01L21/563 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2224/73203 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： Disclosed is a semiconductor wafer, and the method of making the same, the wafer being formed to have a multiplicity of raised contact pads on its surface. The contact pads are formed with conductors which are disposed on the surface of the wafer and which are coupled to internal circuitry embedded in the wafer rough vias in the wafers surface. The contact pads are in a raised elevational relationship relative to the surface conductors. After the wafer is fully processed, by dicing individual integrated circuit chips out of the wafer, each chip can then be mounted on a higher level of assembly, such as a printed circuit board. The raised contact pads originally formed on the wafer, and therefore formed on each individual chip, provide the contact points by which the chip can be bonded with matingly arranged contact pads on the higher level of assembly.
摘要翻译： 公开了一种半导体晶片及其制造方法，晶片形成为在其表面上具有多个凸起的接触焊盘。 接触焊盘由设置在晶片的表面上的导体形成，并且被连接到嵌入在晶片表面中的晶片粗糙过孔中的内部电路。 接触垫相对于表面导体处于升高的高度关系。 在晶片完全处理之后，通过将单个集成电路芯片切割出晶片，每个芯片然后可以安装在诸如印刷电路板的更高级别的组件上。 原来形成在晶片上并因此形成在每个单独芯片上的凸起接触垫提供接触点，通过该接触点，芯片可以在更高级别的组件上配合布置的接触焊盘接合。
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