公开(公告)号：US5691248A

公开(公告)日：1997-11-25

申请号：US507186

申请日：1995-07-26

申请人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L21/304 ,  H01L21/301 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065 ,  H01L21/302

CPC分类号： H01L25/50 ,  H01L21/78 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/10253 ,  Y10S148/028 ,  Y10S438/977

摘要： Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

摘要翻译： 集成电路（“IC”）芯片具有精确定义的边缘和尺寸。 在晶片处理级别，在切口区域中光刻地蚀刻沟槽，以限定晶片上的IC芯片的边缘。 沟槽填充有绝缘材料，并且晶片上的IC芯片完成了上层布线和金属化。 另外的沟槽被定义为填充的先前形成的沟槽。 将晶片从其底部减薄到填充的沟槽，并且去除其中的绝缘材料以将各个IC芯片与晶片分离。 IC芯片边缘定义的精度有助于将IC芯片更容易地堆叠成堆栈，因为不需要许多堆叠级对准过程。

公开(公告)号：US5925924A

公开(公告)日：1999-07-20

申请号：US843177

申请日：1997-04-14

申请人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L21/304 ,  H01L21/301 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065 ,  H01L29/06

CPC分类号： H01L25/50 ,  H01L21/78 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/10253 ,  Y10S148/028 ,  Y10S438/977

摘要： Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

摘要翻译： 集成电路（“IC”）芯片具有精确定义的边缘和尺寸。 在晶片处理级别，在切口区域中光刻地蚀刻沟槽，以限定晶片上的IC芯片的边缘。 沟槽填充有绝缘材料，并且晶片上的IC芯片完成了上层布线和金属化。 另外的沟槽被定义为填充的先前形成的沟槽。 将晶片从其底部减薄到填充的沟槽，并且去除其中的绝缘材料以将各个IC芯片与晶片分离。 IC芯片边缘定义的精度有助于将IC芯片更容易地堆叠成堆栈，因为不需要许多堆叠级对准过程。

公开(公告)号：US5661330A

公开(公告)日：1997-08-26

申请号：US404005

申请日：1995-03-14

申请人： Bruno Roberto Aimi ,  John Edward Cronin ,  Andre Conrad Forcier ,  James Marc Leas ,  Patricia McGuinnes Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： Bruno Roberto Aimi ,  John Edward Cronin ,  Andre Conrad Forcier ,  James Marc Leas ,  Patricia McGuinnes Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L21/82 ,  G01R31/28 ,  H01L21/66 ,  H01L23/52 ,  H01L25/065 ,  H01L29/00

CPC分类号： G01R31/2863 ,  G01R31/2884 ,  H01L22/22 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002

摘要： A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity. The second conductive level includes islands of strap conductors that electrically interconnect the isolated conductors of the first conductive level. The first conductive level and a second conductive level are constructed of different conductive material which may be separately etched so that the second conductive level may be removed without affecting this first conductive level.

摘要翻译： 本发明提供一种具有连接组件的多芯片半导体结构和制造方法，其具有促进烧结应力和结构电气测试的熔断器。 该结构包括具有到其边缘表面的标准传输线的多芯片叠层。 至少一些到边缘表面的导线具有电连接到其上的熔丝，使得在老化应力期间应当产生过大的电流源/漏，相应的保险丝将断开。 还公开了导电结构，其有助于在老化应力和测试之前在多芯片结构的边缘表面上形成最终的可操作的金属化布线。 该导电结构包括第一导电水平和第二导电水平。 第一导电电平具有绝缘导体，其端部紧邻设置。 第二导电电平包括带状导体岛，其电连接第一导电电平的隔离导体。 第一导电水平和第二导电水平由不同的导电材料构成，其可以被单独蚀刻，使得可以去除第二导电水平而不影响该第一导电水平。

公开(公告)号：US06943452B2

公开(公告)日：2005-09-13

申请号：US10103297

申请日：2002-03-21

申请人： Claude Louis Bertin ,  Gordon Arthur Kelley ,  Dennis Arthur Schmidt ,  William Robert Tonti ,  Jerzy Maria Zalesinski

发明人： Claude Louis Bertin ,  Gordon Arthur Kelley ,  Dennis Arthur Schmidt ,  William Robert Tonti ,  Jerzy Maria Zalesinski

IPC分类号： H01L21/768 ,  H01L21/84 ,  H01L23/66 ,  H05K1/02 ,  H05K3/34 ,  H05K3/46 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K1/0221 ,  H01L21/84 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/1903 ,  H01L2924/3011 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09809 ,  H05K2201/09981 ,  H05K2201/10356 ,  H05K2201/10674 ,  H05K2203/061 ,  H01L2924/00

摘要： An integrated circuit is provided that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.

摘要翻译： 提供一种集成电路，其包含至少部分地形成在含硅衬底内的同轴信号线。 同轴信号线包括内部导体，其具有沿着所述长度的外部导体的长度，所述长度被轴向包围并绝缘。 本文还公开了一种制备具有至少部分地形成在含硅衬底内的所述同轴信号线的集成电路的方法。

公开(公告)号：US06388198B1

公开(公告)日：2002-05-14

申请号：US09265098

申请日：1999-03-09

申请人： Claude Louis Bertin ,  Gordon Arthur Kelley ,  Dennis Arthur Schmidt ,  William Robert Tonti ,  Jerzy Maria Zalesinski

发明人： Claude Louis Bertin ,  Gordon Arthur Kelley ,  Dennis Arthur Schmidt ,  William Robert Tonti ,  Jerzy Maria Zalesinski

IPC分类号： H05K109

CPC分类号： H05K1/0221 ,  H01L21/84 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/1903 ,  H01L2924/3011 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09809 ,  H05K2201/09981 ,  H05K2201/10356 ,  H05K2201/10674 ,  H05K2203/061 ,  H01L2924/00

摘要： An integrated circuit that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.

摘要翻译： 一种集成电路，其包含至少部分地形成在含硅衬底内的同轴信号线。 同轴信号线包括内导体，其具有沿着所述长度的外导体沿轴向包围并绝缘的长度。 本文还公开了一种制备具有至少部分地形成在含硅衬底内的所述同轴信号线的集成电路的方法。

公开(公告)号：US5651857A

公开(公告)日：1997-07-29

申请号：US525269

申请日：1995-09-08

申请人： John Edward Cronin ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： John Edward Cronin ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/329 ,  H01L21/336 ,  H01L21/3105

CPC分类号： H01L28/40 ,  H01L21/0337 ,  H01L29/66166 ,  H01L29/66659 ,  Y10S438/947

摘要： Improved film spacers for the sidewalls within semiconductor structures are disclosed. The spacers are made of non-conformal, organic materials, such as polyimides, acrylates, methacrylates, and various photoresist compositions. They are formed on the sidewalls by a process which involves the formation of overhang structures. The film spacers may be used for a variety of applications, such as sidewall imaging, control of dopant diffusion in an FET, formation of borderless contacts, and the manufacture of a resistor from an FET.

摘要翻译： 公开了用于半导体结构内的侧壁的改进的膜间隔物。 间隔件由非共形有机材料制成，例如聚酰亚胺，丙烯酸酯，甲基丙烯酸酯和各种光致抗蚀剂组合物。 它们通过涉及形成悬垂结构的方法形成在侧壁上。 膜间隔物可以用于各种应用，例如侧壁成像，FET中掺杂剂扩散的控制，无边界接触的形成以及来自FET的电阻器的制造。

公开(公告)号：US06242778B1

公开(公告)日：2001-06-05

申请号：US09158813

申请日：1998-09-22

申请人： Patricia McGuinness Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： Patricia McGuinness Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L2701

CPC分类号： H01L27/1203 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a silicon on insulator technology, cooling channels in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer, where the junction regions are separated from the substrate by an insulating layer. In a second embodiment, thermal conductors in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer where the junction regions are separated from the substrate by an insulating layer. Optionally, either the cooling channels or the thermal conductors may be enlarged such that a plurality of devices may be cooled by a single cooling channel or thermal conductor.

摘要翻译： 在绝缘体上硅技术中，支撑衬底中的冷却通道基本上位于半导体层中所选择的各个有源器件的接合区域的下方，其中结区域通过绝缘层与衬底分离。 在第二实施例中，支撑衬底中的热导体基本上位于半导体层中所选择的各个有源器件的接合区域的下方，其中结区域通过绝缘层与衬底分离。 可选地，可以扩大冷却通道或热导体，使得多个装置可以由单个冷却通道或热导体冷却。

公开(公告)号：US5679609A

公开(公告)日：1997-10-21

申请号：US631756

申请日：1996-04-12

申请人： Bruno Roberto Aimi ,  John Edward Cronin ,  Andre Conrad Forcier ,  James Marc Leas ,  Patricia McGuinnes Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： Bruno Roberto Aimi ,  John Edward Cronin ,  Andre Conrad Forcier ,  James Marc Leas ,  Patricia McGuinnes Marmillion ,  Anthony Michael Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L21/82 ,  G01R31/28 ,  H01L21/66 ,  H01L23/52 ,  H01L25/065 ,  H01L21/60

CPC分类号： G01R31/2863 ,  G01R31/2884 ,  H01L22/22 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002

摘要： A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity. The second conductive level includes islands of strap conductors that electrically interconnect the isolated conductors of the first conductive level. The first conductive level and a second conductive level are constructed of different conductive material which may be separately etched so that the second conductive level may be removed without affecting this first conductive level.

公开(公告)号：US5658185A

公开(公告)日：1997-08-19

申请号：US547751

申请日：1995-10-25

申请人： Clifford Owen Morgan, III ,  Dennis Arthur Schmidt ,  Philip Nicholas Theodoseau

发明人： Clifford Owen Morgan, III ,  Dennis Arthur Schmidt ,  Philip Nicholas Theodoseau

IPC分类号： B24B37/16 ,  B24B57/02 ,  B24B1/00 ,  B24C9/00

CPC分类号： B24B37/16 ,  B24B57/02

摘要： An apparatus and method for improving planarity of chemical-mechanical polishing of substrates are provided. The apparatus includes a platen having a planar surface upon which a polishing pad is removably affixed. The pad has an exposed planar surface, and a carrier removably holds the substrate against the planar surface. The apparatus includes a slurry distribution system and a slurry removal system. The slurry distribution system provides slurry to an instantaneous interface area of the substrate and planar surface through the platen and pad, while the slurry removal system removes slurry from the instantaneous interface area through the pad and the platen, notwithstanding rotation of the platen and/or substrate, as well as linear movement of the substrate relative to the rotating platen.

摘要翻译： 提供了一种用于提高基板的化学机械抛光的平面度的装置和方法。 该装置包括具有平面的压板，抛光垫可拆卸地固定在该平面上。 垫具有暴露的平坦表面，并且载体可移除地将基板保持抵靠平面。 该装置包括浆料分配系统和浆料去除系统。 浆料分配系统通过压板和垫将浆料提供到基材和平面表面的瞬时界面区域，同时浆料移除系统通过压板和压板从即时界面区域移除浆料，尽管压板和/或 衬底以及衬底相对于旋转压板的线性移动。